{"id":99396,"updated":"2025-01-21T12:05:51.500314+00:00","links":{},"created":"2025-01-18T23:45:26.044085+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00099396","sets":["1164:2822:7504:7505"]},"path":["7505"],"owner":"11","recid":"99396","title":["統計的手法を用いた並列化コンパイラ協調マルチコアアーキテクチャシミュレータ高速化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-03-08"},"_buckets":{"deposit":"6417af3e-4c2c-46e8-8c9a-05d230ca6ea7"},"_deposit":{"id":"99396","pid":{"type":"depid","value":"99396","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"統計的手法を用いた並列化コンパイラ協調マルチコアアーキテクチャシミュレータ高速化手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"統計的手法を用いた並列化コンパイラ協調マルチコアアーキテクチャシミュレータ高速化手法"},{"subitem_title":"A Parallelizing Compiler Cooperative Acceleration Technique of Multicore Architecture Simulation using a Statistical Method","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"OS及びシステム開発","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-03-08","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学理工学術院"},{"subitem_text_value":"早稲田大学理工学術院"},{"subitem_text_value":"早稲田大学理工学術院"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/99396/files/IPSJ-EMB14032049.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB14032049.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d022cce7-8738-42a4-b89b-f08259209a51","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田口, 学豐"},{"creatorName":"木村, 啓二"},{"creatorName":"笠原, 博徳"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Gakuho, Taguchi","creatorNameLang":"en"},{"creatorName":"Keiji, Kimura","creatorNameLang":"en"},{"creatorName":"Hironori, Kasahara","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では,並列化コンパイラと協調しマルチコアアーキテクチャシミュレーションを高速化する手法を提案する.本手法では,まず実機での逐次実行のプロファイルを取得し,そのプロファイル結果を x-means 法でクラスタリングすることにより,評価対象アーキテクチャの詳細シミュレーションを行う箇所を特定する.さらに,クラスタリングの情報と評価対象マルチコアで実行するアプリケーションから,並列化コンパイラは精度切り替えコードを含む並列化コードを生成する.評価の結果,16 コアのシミュレーションを SPEC ベンチマークの equake において誤差 0.04%で 437 倍,MediaBench の MPEG2 エンコーダにおいて誤差 0.04%で 28 倍の速度向上をそれぞれ得ることが出来た.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A parallelizing compiler cooperative acceleration technique for multicore architecture simulation is proposed in this paper. Profile data of a sequential execution of a target application on a real machine is decomposed into multiple clusters by x-means clustering. Then, sampling points for a detail simulation mode in each cluster are calculated. In addition, a parallelizing compiler generates a parallelized code by taking both of the clustering information and the source code of the target application. The evaluation results show, in the case of the simulation for 16 cores, 437 times speedup is achieved with 0.04% error for equake, and 28 times speedup is achieved with 0.04% error for mpeg2 encoder.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告組込みシステム(EMB)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-03-08","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"49","bibliographicVolumeNumber":"2014-EMB-32"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}