{"created":"2025-01-18T23:45:22.109152+00:00","updated":"2025-01-21T12:06:34.289259+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00099320","sets":["1164:2036:7423:7503"]},"path":["7503"],"owner":"11","recid":"99320","title":["ソフトウェア向けハードウェア性能記述を用いたマルチコアにおける性能見積り"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-03-08"},"_buckets":{"deposit":"689a3de8-f1aa-4e42-82b4-f3078a52bf99"},"_deposit":{"id":"99320","pid":{"type":"depid","value":"99320","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ソフトウェア向けハードウェア性能記述を用いたマルチコアにおける性能見積り","author_link":["0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ソフトウェア向けハードウェア性能記述を用いたマルチコアにおける性能見積り"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサ・ハードウェア","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-03-08","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"名古屋大学"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/99320/files/IPSJ-SLDM14165026.pdf"},"date":[{"dateType":"Available","dateValue":"2016-03-08"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM14165026.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"16bd7d96-b04c-4d8f-8e33-30ce16a85dcf","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"西村裕"},{"creatorName":"中村陸"},{"creatorName":"荒川文男"},{"creatorName":"枝廣正人"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"多種多様なメニーコアアーキテクチャが提案されてきており，今後ますます増える傾向にある．このような状況において，ソフトウェア開発ツール等がアーキテクチャ毎に個別に対応することは非効率である．これをなくすため我々は，マルチ・メニーコア標準プラットフォームの開発を進め，ソフトウェア視点での性能情報を含むハードウェア記述の標準化を提案している．本研究では，組込みメニーコアプロセッサの一つを用い，標準記述による性能見積りと実際の処理時間の差異を評価し，精度を高めるための手法及び課題について述べる．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-03-08","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"26","bibliographicVolumeNumber":"2014-SLDM-165"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":99320,"links":{}}