{"updated":"2025-01-21T12:21:23.322550+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00098709","sets":["1164:2240:7465:7466"]},"path":["7466"],"owner":"11","recid":"98709","title":["ロードバランスを考慮した電力制約下におけるCPUのDVFS制御"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-02-24"},"_buckets":{"deposit":"1ee065b4-8c37-4a30-8232-6725ac3f40a1"},"_deposit":{"id":"98709","pid":{"type":"depid","value":"98709","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ロードバランスを考慮した電力制約下におけるCPUのDVFS制御","author_link":["0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ロードバランスを考慮した電力制約下におけるCPUのDVFS制御"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"電力最適化と性能評価","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-02-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/98709/files/IPSJ-HPC14143023.pdf"},"date":[{"dateType":"Available","dateValue":"2016-02-24"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC14143023.pdf","filesize":[{"value":"663.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"633a731a-efcf-440d-bb54-ab2b929ed3b7","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"會田翔"},{"creatorName":"三輪忍"},{"creatorName":"中村宏"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"現在の大規模計算環境においては，実質的に利用可能な電力の限界が見えてきたことで電力制約が性能向上の妨げとなっている．近年そういった環境下において必要となる性能対電力のトレードオフの調整を行う技術が発達してきた．本稿では，電力効率改善のため，CPU 間のロードバランス改善のためのランタイム制御手法を提案し，最大 21.3%の性能向上を達成した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-02-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"23","bibliographicVolumeNumber":"2014-HPC-143"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:44:54.271532+00:00","id":98709,"links":{}}