{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00098134","sets":["1164:2036:7423:7424"]},"path":["7424"],"owner":"11","recid":"98134","title":["マルチFPGAシステムにおける演算モジュールの配置手法の検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-01-21"},"_buckets":{"deposit":"e4ac99ad-6eef-460e-b459-b63ef8dbeaee"},"_deposit":{"id":"98134","pid":{"type":"depid","value":"98134","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"マルチFPGAシステムにおける演算モジュールの配置手法の検討","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチFPGAシステムにおける演算モジュールの配置手法の検討"},{"subitem_title":"A study on module allocation in multi-FPGA systems","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA応用","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-01-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"琉球大学工学部"},{"subitem_text_value":"琉球大学工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"(独)宇宙航空研究開発機構"},{"subitem_text_value":"琉球大学工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"University of the Ryukyus","subitem_text_language":"en"},{"subitem_text_value":"University of the Ryukyus","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Japan Aerospace Exploration Agency","subitem_text_language":"en"},{"subitem_text_value":"University of the Ryukyus","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/98134/files/IPSJ-SLDM14164017.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM14164017.pdf","filesize":[{"value":"458.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"f881728e-8769-4ebf-a2b6-13ba2f206a49","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"平井, 裕介"},{"creatorName":"仲里, 和晃"},{"creatorName":"MohamedSofianbinAbuTalip"},{"creatorName":"Mishra, Dipikarani"},{"creatorName":"天野, 英晴"},{"creatorName":"藤田, 直行"},{"creatorName":"長名, 保範"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yusuke, HIRAI","creatorNameLang":"en"},{"creatorName":"Kazuaki, Nakazato","creatorNameLang":"en"},{"creatorName":"Mohamed, SofianbinAbuTalip","creatorNameLang":"en"},{"creatorName":"Mishra, Dipikarani","creatorNameLang":"en"},{"creatorName":"Hideharu, Amano","creatorNameLang":"en"},{"creatorName":"Naoyuki, Fujita","creatorNameLang":"en"},{"creatorName":"Yasunori, Osana","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"航空機設計などに用いられる数値計算流体力学など計算科学の諸分野では常に計算機の能力が不足しており、より高性能な計算機が必要とされていろ。そこで、複数の FPGA を利用した科学技術演算高速化の試みとして FLOPS-2D が開発された。しかし、マルチ FPGA システムは演算モジュールの配置や接続関係が実効性能を大きく左右することが知られているため、これを考慮した設計法が必要である。そこで、本研究ではデータフローを自動的に分割して配置し、Simulated Annealing(SA) によって最適化する手法の提案と実装およびその評価を行った。評価には Roe average と MUSCL のネットリストを対象とした。その結果、2×2，4×4の FPGA アレイ上にいずれの場合でも良好な配置ができることを確認した。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Computational fluid dynamics (CFD), a powerful tool for aircraft design and other mechanical designs is a major application in computational science. Since CFD is a CPU intensive application, several challenges have made to accelerate the computation with FPGA. In this report, a method to divide and place a large dataflow of numerical pipeline onto an FPGA array, such as FLOPS-2D. This method reduces the communication bottleneck by optimizing the placement with simulated annealing. Pipelines for Roe average and MUSCL is placed on FPGA arrays on 2 x 2 or 4 x 4 by the proposed method, and the effective results have been obtained.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-01-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"17","bibliographicVolumeNumber":"2014-SLDM-164"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":98134,"updated":"2025-01-21T12:36:52.031427+00:00","links":{},"created":"2025-01-18T23:44:26.694354+00:00"}