{"id":96107,"updated":"2025-01-21T13:27:27.766509+00:00","links":{},"created":"2025-01-18T23:43:03.225972+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00096107","sets":["1164:2036:6976:7313"]},"path":["7313"],"owner":"11","recid":"96107","title":["論理BISＴにおけるスキャンイン電力制御回路のTEG評価について"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-11-20"},"_buckets":{"deposit":"25d4f310-df3b-444b-a605-aa72a870f1f2"},"_deposit":{"id":"96107","pid":{"type":"depid","value":"96107","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"論理BISＴにおけるスキャンイン電力制御回路のTEG評価について","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"論理BISＴにおけるスキャンイン電力制御回路のTEG評価について"},{"subitem_title":"Design and evaluation of circuits to control scan-in power in logic BIST","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"テスト","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2013-11-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州工業大学／独立行政法人科学技術振興機構CREST"},{"subitem_text_value":"九州工業大学"},{"subitem_text_value":"九州工業大学／独立行政法人科学技術振興機構CREST"},{"subitem_text_value":"九州工業大学／独立行政法人科学技術振興機構CREST"},{"subitem_text_value":"九州工業大学／独立行政法人科学技術振興機構CREST"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyushu Institute of Technology / Japan Science and Technology Agency, CREST","subitem_text_language":"en"},{"subitem_text_value":"Kyushu Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Kyushu Institute of Technology / Japan Science and Technology Agency, CREST","subitem_text_language":"en"},{"subitem_text_value":"Kyushu Institute of Technology / Japan Science and Technology Agency, CREST","subitem_text_language":"en"},{"subitem_text_value":"Kyushu Institute of Technology / Japan Science and Technology Agency, CREST","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/96107/files/IPSJ-SLDM13163042.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM13163042.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e93e3b9f-b1d0-48e8-9fc1-7539aee4e254","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"加藤, 隆明"},{"creatorName":"喜納, 猛"},{"creatorName":"三宅, 庸資"},{"creatorName":"佐藤, 康夫"},{"creatorName":"梶原, 誠司"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takaaki, Kato","creatorNameLang":"en"},{"creatorName":"Takeru, Kina","creatorNameLang":"en"},{"creatorName":"Yousuke, Miyake","creatorNameLang":"en"},{"creatorName":"Yasuo, Sato","creatorNameLang":"en"},{"creatorName":"Seiji, Kajihara","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"スキャンベースの論理 BIST では高いテスト時電力の低減が課題となっている．しかしアプリケーション毎にその電力低減目標は異なるので，テスト時電力を低減するだけでなく，それを制御する技術開発が必要である．筆者らの先行研究では，スキャンイン時の ＦＦ のトグル率を制御可能な電力低減回路を提案した．本研究では電力制御回路を用いた具体的な制御手法を提案するとともに，TEG チップに電力制御回路を実装し，実際の電力低減効果の測定評価を行う.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Power reduction during testing with Logic BIST is a crucial problem; however, power controlling techniques are required as well as power reduction techniques because the required power level differs depending on its applications. The authors' previous study has proposed a power reducing circuit that controls toggle rate during scan-in mode. This paper proposes a power controlling method, which is based on the power controlling circuit, and its effectiveness is evaluated by measurement of a TEG that equips the power controlling circuit.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2013-11-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"42","bibliographicVolumeNumber":"2013-SLDM-163"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}