@techreport{oai:ipsj.ixsq.nii.ac.jp:00096107, author = {加藤, 隆明 and 喜納, 猛 and 三宅, 庸資 and 佐藤, 康夫 and 梶原, 誠司 and Takaaki, Kato and Takeru, Kina and Yousuke, Miyake and Yasuo, Sato and Seiji, Kajihara}, issue = {42}, month = {Nov}, note = {スキャンベースの論理 BIST では高いテスト時電力の低減が課題となっている.しかしアプリケーション毎にその電力低減目標は異なるので,テスト時電力を低減するだけでなく,それを制御する技術開発が必要である.筆者らの先行研究では,スキャンイン時の FF のトグル率を制御可能な電力低減回路を提案した.本研究では電力制御回路を用いた具体的な制御手法を提案するとともに,TEG チップに電力制御回路を実装し,実際の電力低減効果の測定評価を行う., Power reduction during testing with Logic BIST is a crucial problem; however, power controlling techniques are required as well as power reduction techniques because the required power level differs depending on its applications. The authors' previous study has proposed a power reducing circuit that controls toggle rate during scan-in mode. This paper proposes a power controlling method, which is based on the power controlling circuit, and its effectiveness is evaluated by measurement of a TEG that equips the power controlling circuit.}, title = {論理BISTにおけるスキャンイン電力制御回路のTEG評価について}, year = {2013} }