{"created":"2025-01-18T23:43:02.378212+00:00","updated":"2025-01-21T13:26:58.938806+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00096090","sets":["1164:2036:6976:7313"]},"path":["7313"],"owner":"11","recid":"96090","title":["細粒度パワーゲーテイングを実装したCPU \"Geyser-3\"の開発と温度に適応した電源遮断制御"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-11-20"},"_buckets":{"deposit":"aaadc206-62a0-462f-89d5-6ee99e2fde37"},"_deposit":{"id":"96090","pid":{"type":"depid","value":"96090","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"細粒度パワーゲーテイングを実装したCPU \"Geyser-3\"の開発と温度に適応した電源遮断制御","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"細粒度パワーゲーテイングを実装したCPU \"Geyser-3\"の開発と温度に適応した電源遮断制御"},{"subitem_title":"Development of a fine-grain power-gated CPU \"Geyser-3\" and adaptive power-off control to the temperature","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"低消費電力技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2013-11-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"東京農工大学"},{"subitem_text_value":"東京農工大学"},{"subitem_text_value":"電気通信大学"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"The University of Electro-Communications","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/96090/files/IPSJ-SLDM13163025.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM13163025.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"127af43d-7b92-45f0-8490-be13b7fed225","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"宇佐美, 公良"},{"creatorName":"工藤, 優"},{"creatorName":"松永, 健作"},{"creatorName":"小坂, 翼"},{"creatorName":"鶴井, 敬大"},{"creatorName":"王, 蔚涵"},{"creatorName":"天野, 英晴"},{"creatorName":"坂本, 龍一"},{"creatorName":"並木, 美太郎"},{"creatorName":"近藤, 正章"},{"creatorName":"中村, 宏"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kimiyoshi, Usami","creatorNameLang":"en"},{"creatorName":"Masaru, Kudo","creatorNameLang":"en"},{"creatorName":"Kensaku, Matsunaga","creatorNameLang":"en"},{"creatorName":"Tsubasa, Kosaka","creatorNameLang":"en"},{"creatorName":"Yoshihiro, Tsurui","creatorNameLang":"en"},{"creatorName":"Weihan, Wang","creatorNameLang":"en"},{"creatorName":"Hideharu, Amano","creatorNameLang":"en"},{"creatorName":"Ryuichi, Sakamoto","creatorNameLang":"en"},{"creatorName":"Mitaro, Namiki","creatorNameLang":"en"},{"creatorName":"Masaaki, Kondo","creatorNameLang":"en"},{"creatorName":"Hiroshi, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"内部の演算器に対して細粒度のパワーゲーテイングを行う 32-bit CPU \"Geyser-3\" のチップ実装について述べるとともに、オンチップ・リークモニタ回路と OS を使って、温度変動に応じてエネルギーを最小にする電源遮断制御手法を提案する。65nm CMOS プロセスで試作したチップで、5つのベンチマークプログラムを走らせて評価した結果､パワーゲーテイングを行わない場合に比べ､温度 25℃～85℃で､動作時の消費エネルギーが 21～35％ にまで低減することを観測した。さらに、この温度範囲で、従来の細粒度パワーゲーテイング手法に比べ、消費エネルギーが最大で 15％低減することが分かった。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper describes a design and control scheme of a microprocessor whose internal function units are powergated at instruction-by-instruction basis. Enabling/disabling the power gating is adaptively controlled under the support of on-chip leakage monitors and the operating system to minimize energy overhead due to sleep-in and wakeup. Measured results of the fabricated chip in the 65nm CMOS technology demonstrated that our approach reduces energy to 21-35% for the range of 25-85℃ as compared to non power-gated case. Energy dissipation was reduced by up to 15% as compared to the conventional fine-grain power gating technique in the same temperature range.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2013-11-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"25","bibliographicVolumeNumber":"2013-SLDM-163"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":96090,"links":{}}