{"updated":"2025-01-21T13:34:11.958552+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00095343","sets":["1164:2036:6976:7275"]},"path":["7275"],"owner":"11","recid":"95343","title":["製造後遅延調整機能を持つRDRアーキテクチャ向け高位合成手法の評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-09-30"},"_buckets":{"deposit":"c0d84b77-48ae-4910-a8d8-61297eacf351"},"_deposit":{"id":"95343","pid":{"type":"depid","value":"95343","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"製造後遅延調整機能を持つRDRアーキテクチャ向け高位合成手法の評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"製造後遅延調整機能を持つRDRアーキテクチャ向け高位合成手法の評価"},{"subitem_title":"A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2013-09-30","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/95343/files/IPSJ-SLDM13162009.pdf","label":"IPSJ-SLDM13162009"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM13162009.pdf","filesize":[{"value":"887.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"8db598fa-a8cf-4bdc-aa0b-84ba6b018e97","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"萩尾, 勇太"},{"creatorName":"柳澤, 政生"},{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuta, Hagio","creatorNameLang":"en"},{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"},{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"LSI の微細加工技術の進歩により配線遅延の拡大や製造時の遅延ばらつきによるタイミング違反が問題となっている．とりわけ配線遅延がゲート遅延と比較して相対的に増加しており高位合成段階でいかに配線遅延を取り扱うかが鍵となる．また，製造時の遅延ばらつきに対応するために，従来は過剰なマージンの挿入，統計的静的遅延解析などが適用されてきたが，性能低下しない手法としてチップ製造後の回路チューニングが提案されている．このような背景に基づき，配線遅延の拡大や製造時の遅延ばらつきの双方に対応した高位合成として，製造後遅延調整機能を持つ RDR アーキテクチャ向け高位合成手法を提案した．本稿では，提案手法の有効'性を検証するため計算機実験をし，従来手法と比較することで提案手法を評価する．また，回路面積を最小化するために提案手法では類似化のステップを設けているが，その有効性についても検証する．計算機実験により，提案手法は従来手法と比較して遅延ばらつき発生時の実行時間を最大 42.9％ 削減できることを確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. Thus, we have proposed a high-level synthesis algorithm with post-silicon delay tuning for RDR architectures. In this paper, we evaluate our high-level synthesis algorithm comparing several existing algorithms considering several situations. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2013-09-30","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"9","bibliographicVolumeNumber":"2013-SLDM-162"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:42:27.587396+00:00","id":95343,"links":{}}