Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling

• Item type: Trans(1)
• 公開日: 2013-08-05
• タイトル: Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling
• タイトル / 言語: en
• タイトル: Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [Behavioral Synthesis] HDR, clock gating, concurrency-oriented scheduling, clock tree, clock gating timing
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Electronic and Photonic Systems, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Electronic and Photonic Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者名: Hiroyuki, Akasaka; Shin-yaAbe; Masao, Yanagisawa; Nozomu, Togawa
• 著者名(英): Hiroyuki, Akasaka; Shin-ya, Abe; Masao, Yanagisawa; Nozomu, Togawa
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: With the miniaturization of LSIs and its increasing performance, demand for high-functional portable devices has grown significantly. At the same time, battery lifetime and device overheating are leading to major design problems hampering further LSI integration. On the other hand, the ratio of an interconnection delay to a gate delay has continued to increase as device feature size decreases. We have to estimate interconnection delays and reduce energy consumption even in a high-level synthesis stage. In this paper, we propose a high-level synthesis algorithm for huddle-based distributed-register architectures (HDR architectures) with clock gatings based on concurrency-oriented scheduling/functional unit binding. We assume coarse-grained clock gatings to huddles and we focus on the number of control steps, or gating steps, at which we can apply the clock gating to registers in every huddle. We propose two methods to increase gating steps: One is that we try to schedule and bind operations to be performed at the same timing. By adjusting the clock gating timings in a high-level synthesis stage, we expect that we can enhance the effect of clock gatings more than applying clock gatings after logic synthesis. The other is that we try to synthesize huddles such that each of the synthesized huddles includes registers which have similar or the same clock gating timings. At this time, we determine the clock gating timings to minimize all energy consumption including clock tree energy. The experimental results show that our proposed algorithm reduces energy consumption by a maximum of 23.8% compared with several conventional algorithms.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: With the miniaturization of LSIs and its increasing performance, demand for high-functional portable devices has grown significantly. At the same time, battery lifetime and device overheating are leading to major design problems hampering further LSI integration. On the other hand, the ratio of an interconnection delay to a gate delay has continued to increase as device feature size decreases. We have to estimate interconnection delays and reduce energy consumption even in a high-level synthesis stage. In this paper, we propose a high-level synthesis algorithm for huddle-based distributed-register architectures (HDR architectures) with clock gatings based on concurrency-oriented scheduling/functional unit binding. We assume coarse-grained clock gatings to huddles and we focus on the number of control steps, or gating steps, at which we can apply the clock gating to registers in every huddle. We propose two methods to increase gating steps: One is that we try to schedule and bind operations to be performed at the same timing. By adjusting the clock gating timings in a high-level synthesis stage, we expect that we can enhance the effect of clock gatings more than applying clock gatings after logic synthesis. The other is that we try to synthesize huddles such that each of the synthesized huddles includes registers which have similar or the same clock gating timings. At this time, we determine the clock gating timings to minimize all energy consumption including clock tree energy. The experimental results show that our proposed algorithm reduces energy consumption by a maximum of 23.8% compared with several conventional algorithms.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 6, p. 101-111, 発行日 2013-08-05
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会