{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00094573","sets":["1164:1579:7041:7232"]},"path":["7232"],"owner":"11","recid":"94573","title":["値予測用投機実行回路によるキャッシュコヒーレンシ機構の高速化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-07-24"},"_buckets":{"deposit":"c9a54ed9-38d2-4f7b-a884-cedc2f6e584d"},"_deposit":{"id":"94573","pid":{"type":"depid","value":"94573","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"値予測用投機実行回路によるキャッシュコヒーレンシ機構の高速化","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"値予測用投機実行回路によるキャッシュコヒーレンシ機構の高速化"},{"subitem_title":"Accelerating Cache Coherence Mechanism with Speculation Circuit for Value Prediction","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"キャッシュ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2013-07-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/94573/files/IPSJ-ARC13206019.pdf"},"date":[{"dateType":"Available","dateValue":"2015-07-24"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC13206019.pdf","filesize":[{"value":"803.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"0faacff4-19d1-4155-a86c-899a96455bb0","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"大野, 純"},{"creatorName":"平木, 敬"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jun, Ohno","creatorNameLang":"en"},{"creatorName":"Kei, Hiraki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"マルチコア・メニーコアシステムにおいてキャッシュコヒーレンシを保つための手法としてディレクトリ機構が一般的になりつつある。しかしながらディレクトリ機構はコア数の増加に伴う容量の問題や 3 hop アクセスによるレイテンシの増加といった欠点がある。一方ディレクトリを必要としない手法として、同期のタイミングで各コアが自発的に L1 のキャッシュを無効化する手法が提案されている。この手法では、実際には他のコアによって上書きされていないキャッシュラインが同期のタイミングで無効化されてしまう問題がある。本研究では値予測とともに用いられる投機実行回路により、これらのキャッシュラインの値を用いて投機実行することでキャッシュコヒーレンシ機構の高速化を図った。結果として複雑な予測機構を用いずに平均で28%高速化することができた。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Directory is one of the common method to maintain cache coherence in multi/manycore systems. However, directory has problems in area and latency especially in systems with large number of cores. Conversely, directoryless protocol, where each core invalidates their own L1 cache lines at the time of synchronization is proposed. The problem of this method is that the cache lines which are not written by another core are invalidated at synchronization point. We accelerate the coherence mechanism by speculatively executing on these cache lines with speculation circuit for value prediction. Our result shows 28% acceleration on average without complicated prediction schemes.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2013-07-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19","bibliographicVolumeNumber":"2013-ARC-206"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"updated":"2025-01-21T14:32:52.719822+00:00","created":"2025-01-18T23:41:51.620579+00:00","links":{},"id":94573}