{"created":"2025-01-18T23:41:51.172095+00:00","updated":"2025-01-21T14:32:35.248234+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00094564","sets":["1164:1579:7041:7232"]},"path":["7232"],"owner":"11","recid":"94564","title":["ハードウェアトランザクショナルメモリのアーキテクチャに依存しない評価システム"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-07-24"},"_buckets":{"deposit":"b3c84661-12ad-4f1c-b0b4-df931d4cf0b5"},"_deposit":{"id":"94564","pid":{"type":"depid","value":"94564","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ハードウェアトランザクショナルメモリのアーキテクチャに依存しない評価システム","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ハードウェアトランザクショナルメモリのアーキテクチャに依存しない評価システム"},{"subitem_title":"Architecture-Independent Hardware Transactional Memory Evaluation System","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"投機","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2013-07-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo.","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/94564/files/IPSJ-ARC13206010.pdf"},"date":[{"dateType":"Available","dateValue":"2015-07-24"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC13206010.pdf","filesize":[{"value":"257.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9d485f71-d90f-443e-b7e1-e8cf5da25531","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"吉山, 悠爾"},{"creatorName":"平木, 敬"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuji, Yoshiyama","creatorNameLang":"en"},{"creatorName":"Kei, Hiraki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"並列処理の普及により並行性制御はますます重要になっている一方，並行性制御の手法としてトランザクショナルメモリと呼ばれる手法が提案されている。ハードウエアトランザクショナルメモリ (HTM) はトランザクショナルメモリをハードウェアにより実現したものであり，HTM を実装したいくつかの商用プロセッサが登場している。しかしながら，HTM においては統一的なパフォーマンス評価手法が確立されているとはいえず，またそのパフォーマンスがアーキテクチャに依存しやすいため評価手法を確立しにくい。我々は FPGA 上へ単純で拡張性の高いプロセッサを実装することで，アーキテクチャに依存しない HTM のための統一的な評価環境を構築する。これにより，様々な HTM の構成法を簡単に素早く評価できるようになるだろう。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"While the concurrency control is more important to diffuse the parallel processing, transactional memory is proposed as concurrency control methods. Hardware transactional memory (HTM) is transactional memory to be implemented by hardware; some commercial processors have HTM system. However, performance evaluation methods for HTM are not established. Furthermore, it is hard because HTM performance depends on HTM architecture. We design and implement the high extensibility processor on FPGA chips, and we construct the comprehensive evaluation system for HTM. Thus, we are able to evaluate the various hardware transactional memory systems easily and quickly.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2013-07-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"10","bibliographicVolumeNumber":"2013-ARC-206"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":94564,"links":{}}