{"id":94377,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00094377","sets":["581:7002:7225"]},"path":["7225"],"owner":"11","recid":"94377","title":["Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-07-15"},"_buckets":{"deposit":"2555c7d5-2400-4fe7-a649-1c29a25ef716"},"_deposit":{"id":"94377","pid":{"type":"depid","value":"94377","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing","author_link":["358578","358577","358584","358582","358579","358580","358585","358583","358581","358586"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing"},{"subitem_title":"Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[特集：組込みシステム工学] image processing, reconfigurable processor","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2013-07-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology"},{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology"},{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology"},{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology"},{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Communications and Integrated Systems, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"publish_status":"0","weko_shared_id":11,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/94377/files/IPSJ-JNL5407002.pdf","label":"IPSJ-JNL5407002"},"date":[{"dateType":"Available","dateValue":"2015-07-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL5407002.pdf","filesize":[{"value":"876.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e67f1617-982c-4538-a63e-2d894d885613","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hsuan-ChunLiao"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Mochamad, Asri"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsuyoshi, Isshiki"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Dongju, Li"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Kunieda"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hsuan-Chun, Liao","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Mochamad, Asri","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsuyoshi, Isshiki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Dongju, Li","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Kunieda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"An image processing engine is an important component in generating high quality images in video systems. Processing during capture and display are non-standard and vary from case by case, hence, the flexibility of image processing engines has turned out to be an important issue. The conventional hardware type of image processing engine such as an Application Specific Integrated Circuit (ASIC) is not applicable for this case. In order to increase design reusability and ease time-to-market pressures, Application Specific Instruction-set Processors (ASIP) which provide high flexibility and high computational efficiency have emerged as a promising solution. In this paper, we present two ASIPs. PXL ASIP, which has a reconfigurable multi bank memory module and an SIMD type computation pipeline, is designed for pixel level image processing, while 2D ASIP, which has slide register module and reconfigurable ALU modules, is designed for 2D image processing. PXL ASIP can perform 4 to 10 times faster compared to its base processor, and 2D ASIP can perform 5 to 43 times faster compared to its base processor.\n\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.21(2013) No.3 (online)\nDOI　http://dx.doi.org/10.2197/ipsjjip.21.552\n------------------------------","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"An image processing engine is an important component in generating high quality images in video systems. Processing during capture and display are non-standard and vary from case by case, hence, the flexibility of image processing engines has turned out to be an important issue. The conventional hardware type of image processing engine such as an Application Specific Integrated Circuit (ASIC) is not applicable for this case. In order to increase design reusability and ease time-to-market pressures, Application Specific Instruction-set Processors (ASIP) which provide high flexibility and high computational efficiency have emerged as a promising solution. In this paper, we present two ASIPs. PXL ASIP, which has a reconfigurable multi bank memory module and an SIMD type computation pipeline, is designed for pixel level image processing, while 2D ASIP, which has slide register module and reconfigurable ALU modules, is designed for 2D image processing. PXL ASIP can perform 4 to 10 times faster compared to its base processor, and 2D ASIP can perform 5 to 43 times faster compared to its base processor.\n\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.21(2013) No.3 (online)\nDOI　http://dx.doi.org/10.2197/ipsjjip.21.552\n------------------------------","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicIssueDates":{"bibliographicIssueDate":"2013-07-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"54"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"updated":"2025-01-20T06:47:53.808504+00:00","created":"2025-01-18T23:41:41.995943+00:00","links":{}}