{"updated":"2025-01-21T15:06:13.956677+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00092269","sets":["6164:6165:6426:7175"]},"path":["7175"],"owner":"11","recid":"92269","title":["低消費電力プロセッサのための限定的動的再構成アーキテクチャの提案"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-05-15"},"_buckets":{"deposit":"ad098936-908d-4856-8107-f560e5d0ff71"},"_deposit":{"id":"92269","pid":{"type":"depid","value":"92269","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"低消費電力プロセッサのための限定的動的再構成アーキテクチャの提案","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"低消費電力プロセッサのための限定的動的再構成アーキテクチャの提案"},{"subitem_title":"A Restricted Dynamically Reconfigurable Architecture for Low Power Processors","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"リコンフィギャラブルコンピューティング","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2013-05-15","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"北海道大学"},{"subitem_text_value":"北海道大学"},{"subitem_text_value":"北海道大学"},{"subitem_text_value":"北海道大学"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Hokkaido University","subitem_text_language":"en"},{"subitem_text_value":"Hokkaido University","subitem_text_language":"en"},{"subitem_text_value":"Hokkaido University","subitem_text_language":"en"},{"subitem_text_value":"Hokkaido University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/92269/files/IPSJ-SACSIS2013052.pdf"},"date":[{"dateType":"Available","dateValue":"2015-05-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SACSIS2013052.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"330","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"16"},{"tax":["include_tax"],"price":"330","billingrole":"11"},{"tax":["include_tax"],"price":"330","billingrole":"14"},{"tax":["include_tax"],"price":"330","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e1555e1d-ab44-4203-8bd4-df0f19a654ea","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"平尾, 岳志"},{"creatorName":"安達, 琢"},{"creatorName":"浅井, 哲也"},{"creatorName":"本村, 真人"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takeshi, Hirao","creatorNameLang":"en"},{"creatorName":"Taku, Adachi","creatorNameLang":"en"},{"creatorName":"Tetsuya, Asai","creatorNameLang":"en"},{"creatorName":"Masato, Motomura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"高性能・高エネルギー効率のプロセッサを実現するアプローチとして、対象プログラムのホットパスを可変構造のデータパスにマッピングしアクセラレートするリコンフィギュラブルプロセッサが注目されている。本稿では、処理の内容が多岐にわたり、かつ低消費電力性が強く求められる組込み用途をターゲットとし、Control-Flow Driven Data-Flow Switching (CDDS)可変データパスアーキテクチャを提案する。このアーキテクチャは、(1)動的再構成を必要最小限な範囲に限定することで、柔軟性と低消費電力性の両立を目指す、(2)既存命令列をそのままデータパスにマッピングすることで、既存アーキテクチャからスムーズに移行可能なリコンフィギュラブルプロセッサを目指す、の2点をその特徴とする。予備的な評価として、小規模なプログラムを手動マッピングし、その基本的特性を調査した。","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Reconfigurable Processor (RP) has attracted wide attention as an approach to realize high-performance and highly energy-efficient processors by mapping target program's hotpath to a reconfigurable data path. In this paper, we propose Control-Flow Driven Data-Flow Switching(CDDS) variable data path architecture for embedded applications that demand extremely low power consumption and wide-range of usage. This Architecture is characterized by following two features. (1)Aiming to achieve both flexibility and low power consumption by limiting the scope of dynamic reconfiguration, (2)Aiming to smooth migration from the existing architecture by mapping the existing instruction sequence to the data path. As a preliminary evaluation, we have manually mapped small programs to understand fundamental characteristics of the proposed architecture.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"205","bibliographic_titles":[{"bibliographic_title":"先進的計算基盤システムシンポジウム論文集"}],"bibliographicPageStart":"197","bibliographicIssueDates":{"bibliographicIssueDate":"2013-05-15","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2013"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:41:13.207406+00:00","id":92269,"links":{}}