{"updated":"2025-01-21T15:06:09.270453+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00092265","sets":["6164:6165:6426:7175"]},"path":["7175"],"owner":"11","recid":"92265","title":["アドレス情報を利用した並列度の局所的低減によるハードウェアトランザクショナルメモリの高速化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-05-15"},"_buckets":{"deposit":"3e08b4a3-da20-4922-9b15-a4fae6b67aa3"},"_deposit":{"id":"92265","pid":{"type":"depid","value":"92265","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"アドレス情報を利用した並列度の局所的低減によるハードウェアトランザクショナルメモリの高速化","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"アドレス情報を利用した並列度の局所的低減によるハードウェアトランザクショナルメモリの高速化"},{"subitem_title":"A Speed-Up Technique for Hardware Transactional Memories by Reducing Concurrency Considering Conflicting Addresses","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"マルチコア・メニーコア","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2013-05-15","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学／現在，東海旅客鉄道株式会社"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology / Presently with Central Japan Railway Company","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/92265/files/IPSJ-SACSIS2013048.pdf"},"date":[{"dateType":"Available","dateValue":"2015-05-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SACSIS2013048.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"330","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"16"},{"tax":["include_tax"],"price":"330","billingrole":"11"},{"tax":["include_tax"],"price":"330","billingrole":"14"},{"tax":["include_tax"],"price":"330","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"1e60545b-879e-4388-b1f0-41e1c6227f80","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"橋本, 高志良"},{"creatorName":"江藤, 正通"},{"creatorName":"堀場, 匠一朗"},{"creatorName":"津邑, 公暁"},{"creatorName":"松尾, 啓志"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Koshiro, Hashimoto","creatorNameLang":"en"},{"creatorName":"Masamichi, Eto","creatorNameLang":"en"},{"creatorName":"Shoichiro, Horiba","creatorNameLang":"en"},{"creatorName":"Tomoaki, Tsumura","creatorNameLang":"en"},{"creatorName":"Hiroshi, Matsuo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"マルチコア環境では，一般的にロックを用いて共有変数へのアクセスを調停する．しかし，ロックには並列性の低下やデッドロックの発生などの問題があるため，これに代わる並行性制御機構としてトランザクショナル・メモリが提案されている．この機構においては，アクセス競合が発生しない限りトランザクションが投機的に実行されるため，一般にロックよりも並列性が向上する．しかし，Readafter-Readアクセスが発生した際に投機実行を継続した場合，その後に発生するストールが完全に無駄となる場合がある．本稿では，このような問題を引き起こすRead-after-Readアクセスを検出し，それに関与するトランザクションを敢えて逐次実行することで，全体性能を向上させる手法を提案する．シミュレーションによる評価の結果，提案手法により最大66.9%の高速化を確認した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Lock-based thread synchronization techniques are commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilities. Hence, Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TM, transactions are executed speculatively unless a memory access conflict is caused, hence the performance of TM is generally better than that of lock. However, if speculative execution is continued when a Read-after-Read (RaR) access occurs, following stalls can be wasted. In this paper, we propose a speed-up technique by reducing concurrency considering conflicting addresses. The result of the experiment shows that proposed method improves the performance 66.9% in maximum.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"169","bibliographic_titles":[{"bibliographic_title":"先進的計算基盤システムシンポジウム論文集"}],"bibliographicPageStart":"162","bibliographicIssueDates":{"bibliographicIssueDate":"2013-05-15","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2013"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:41:13.007430+00:00","id":92265,"links":{}}