{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00091041","sets":["1164:3925:7119:7120"]},"path":["7120"],"owner":"11","recid":"91041","title":["公開鍵暗号ハードウェアのための多ビット乗算器について"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-03-07"},"_buckets":{"deposit":"703157e0-5b1f-4cd1-9364-cb78a7a6d2f2"},"_deposit":{"id":"91041","pid":{"type":"depid","value":"91041","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"公開鍵暗号ハードウェアのための多ビット乗算器について","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"公開鍵暗号ハードウェアのための多ビット乗算器について"},{"subitem_title":"On A Large-scale Multiplier for Public Key Cryptographic Hardware","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"暗号・暗号実装","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2013-03-07","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"公立はこだて未来大学"},{"subitem_text_value":"公立はこだて未来大学"},{"subitem_text_value":"公立はこだて未来大学"},{"subitem_text_value":"公立はこだて未来大学"},{"subitem_text_value":"公立はこだて未来大学"},{"subitem_text_value":"公立はこだて未来大学"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/91041/files/IPSJ-CSEC13060008.pdf"},"date":[{"dateType":"Available","dateValue":"2015-03-07"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-CSEC13060008.pdf","filesize":[{"value":"901.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"30"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"ee504b25-5009-4675-bf09-a9b7a651b0c6","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"白勢, 政明"},{"creatorName":"木村, 圭吾"},{"creatorName":"村山, 広行"},{"creatorName":"加藤, 翔"},{"creatorName":"小林, 悠太"},{"creatorName":"畠山, 遼平"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masaaki, Shirase","creatorNameLang":"en"},{"creatorName":"Keigo, Kimura","creatorNameLang":"en"},{"creatorName":"Hiroyuki, Murayama","creatorNameLang":"en"},{"creatorName":"Shou, Kato","creatorNameLang":"en"},{"creatorName":"Yuta, Kobayashi","creatorNameLang":"en"},{"creatorName":"Ryohei, Hatakeyama","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11235941","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"多くの公開鍵暗号は多ビット整数乗算を必須とするため，乗算器の性能はそれらのためのハードウェアの性能に影響を与える．Wallace tree 乗算器は，ビット数を n とし配線遅延を無視すると，処理時間は log n に比例する．従って例えば，正しく設計するならば 64 ビット乗算器と 128 ビット乗算器との処理時間の差は理論的にはわずかである．本稿は，配線遅延以外の性能が予定通りとなり，ハードウェアの記述が容易な，更にパイプライン化が容易な，任意のビット数の Wallace tree 乗算器の構成法を提案する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Performance of multipliers influences one of hardwares for many public key cryptographies because such cryptographies require many large-bit integer multiplications. It is known that processing time of n bit Wallace tree multiplier is proportional to log n ignoring wiring delay. Therefore, the difference between processing time of 64 bit multiplier and one of 128 bit multiplier is a little in theory when multipliers are correctly designed. This paper proposes a design method of Wallace tree multiplier with arbitrary bit which has easy hardware description and correctness, and can be easily pipelined.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告コンピュータセキュリティ（CSEC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2013-03-07","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicVolumeNumber":"2013-CSEC-60"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":91041,"updated":"2025-01-21T15:43:56.598930+00:00","links":{},"created":"2025-01-18T23:40:24.957736+00:00"}