{"updated":"2025-01-21T15:53:33.342074+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00090682","sets":["1164:2822:7101:7102"]},"path":["7102"],"owner":"11","recid":"90682","title":["リアルタイム組込みシステム向けのリソースパーティショニング用ハードウェア支援技術の開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-03-06"},"_buckets":{"deposit":"6285cbc9-3524-4bcb-90a0-13d1c9806a7b"},"_deposit":{"id":"90682","pid":{"type":"depid","value":"90682","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"リアルタイム組込みシステム向けのリソースパーティショニング用ハードウェア支援技術の開発","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"リアルタイム組込みシステム向けのリソースパーティショニング用ハードウェア支援技術の開発"},{"subitem_title":"Hardware Support for Resource Partitioning in Real-Time Embedded System","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサ・ハードウェア","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2013-03-06","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"(株)日立製作所中央研究所"},{"subitem_text_value":"(株)日立製作所中央研究所"},{"subitem_text_value":"(株)日立製作所中央研究所"},{"subitem_text_value":"(株)日立製作所中央研究所"},{"subitem_text_value":"(株)日立製作所中央研究所"},{"subitem_text_value":"(株)日立製作所中央研究所"},{"subitem_text_value":"(株)日立製作所中央研究所"},{"subitem_text_value":"ルネサスエレクトロニクス㈱"},{"subitem_text_value":"ルネサスエレクトロニクス㈱"},{"subitem_text_value":"東京農工大学大学院工学研究院"},{"subitem_text_value":"東京農工大学大学院工学研究院"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Hitachi Ltd., Central Research Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd., Central Research Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd., Central Research Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd., Central Research Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd., Central Research Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd., Central Research Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd., Central Research Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Renesas Electronics Corporation","subitem_text_language":"en"},{"subitem_text_value":"Renesas Electronics Corporation","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology, Graduate School of Engineering","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology, Graduate School of Engineering","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/90682/files/IPSJ-EMB13028028.pdf"},"date":[{"dateType":"Available","dateValue":"2015-03-06"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB13028028.pdf","filesize":[{"value":"798.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"c877d0b8-1014-45a0-bd04-86b104d34033","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"本村, 哲朗"},{"creatorName":"近藤, 雄樹"},{"creatorName":"山田, 哲也"},{"creatorName":"高田, 雅士"},{"creatorName":"仁藤, 拓実"},{"creatorName":"野尻, 徹"},{"creatorName":"十山, 圭介"},{"creatorName":"斎藤, 靖彦"},{"creatorName":"西, 博史"},{"creatorName":"佐藤, 未来子"},{"creatorName":"並木, 美太郎"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tetsuro, Honmura","creatorNameLang":"en"},{"creatorName":"Yuki, Kondoh","creatorNameLang":"en"},{"creatorName":"Tetsuya, Yamada","creatorNameLang":"en"},{"creatorName":"Masashi, Takada","creatorNameLang":"en"},{"creatorName":"Takumi, Nitoh","creatorNameLang":"en"},{"creatorName":"Tohru, Nojiri","creatorNameLang":"en"},{"creatorName":"Keisuke, Toyama,","creatorNameLang":"en"},{"creatorName":"Yasuhiko, Saitoh","creatorNameLang":"en"},{"creatorName":"Hirofumi, Nishi","creatorNameLang":"en"},{"creatorName":"Mikiko, Satoh","creatorNameLang":"en"},{"creatorName":"Mitaro, Namiki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"今日の組込みシステムは，リアルタイム制御と情報処理のような独立の複数の機能を扱う必要があり，マルチコア上への搭載が有効である．この時，リソース保護のため，仮想化の一技術であるリソースパーティショニングが必要となる．我々は，リアルタイム性の実現に向けリソースパーティショニングのオーバヘッドを削減する，ハードウェア支援技術ExVisor/XVSを開発した．その主要技術は物理アドレス管理モジュールPAM*で，組込みシステムのメモリ利用方法の特徴を活かした階層のないページテーブルによるダイレクトなアドレス変換で高速化を図る．RTLシミュレーションとFPGA実装で評価を行った結果，シングルコアと比較してリソースアクセス時のオーバヘッドは高々5.6％であることを確認した．*PAM : Physical Address Management module","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Today's embedded systems require multiple functions such as real-time control and information technology and integrating these functions on a multi-core processor is one effective solution. However, this increases overhead as it is necessary to partition resources in this approach to protect them. We developed hardware support called ExVisor/XVS to reduce the overhead of partitioning resources to achieve real-time characteristics. This features a physical address management module (PAM) that uses direct address translation by using a single level page table based on an embedded system's memory usage. We evaluated the overhead in a virtual machine's (VM) resource access through register transfer level (RTL) simulation and implementation on a field-programmable gate array (FPGA), and it was only less than 5.6% compared with the resource access time by a single core processor.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告組込みシステム（EMB）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2013-03-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"28","bibliographicVolumeNumber":"2013-EMB-28"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:40:10.877290+00:00","id":90682,"links":{}}