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An FPGA Implementation of a HOG-based Object Detection Processor
https://ipsj.ixsq.nii.ac.jp/records/90523
https://ipsj.ixsq.nii.ac.jp/records/90523047a6f6f-bc8a-4c84-854f-b2ccfd1843fb
名前 / ファイル | ライセンス | アクション |
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Copyright (c) 2013 by the Information Processing Society of Japan
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オープンアクセス |
Item type | Trans(1) | |||||||
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公開日 | 2013-02-15 | |||||||
タイトル | ||||||||
タイトル | An FPGA Implementation of a HOG-based Object Detection Processor | |||||||
タイトル | ||||||||
言語 | en | |||||||
タイトル | An FPGA Implementation of a HOG-based Object Detection Processor | |||||||
言語 | ||||||||
言語 | eng | |||||||
キーワード | ||||||||
主題Scheme | Other | |||||||
主題 | [Architectural Design] image recognition, histograms of oriented gradients, support vector machine, hardware implementation | |||||||
資源タイプ | ||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
資源タイプ | journal article | |||||||
著者所属 | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属 | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属 | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属 | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属 | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属 | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Graduate School of Engineering, Kobe University | ||||||||
著者名 |
Kosuke, Mizuno
Yosuke, Terachi
Kenta, Takagi
Shintaro, Izumi
Hiroshi, Kawaguchi
Masahiko, Yoshimoto
× Kosuke, Mizuno Yosuke, Terachi Kenta, Takagi Shintaro, Izumi Hiroshi, Kawaguchi Masahiko, Yoshimoto
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著者名(英) |
Kosuke, Mizuno
Yosuke, Terachi
Kenta, Takagi
Shintaro, Izumi
Hiroshi, Kawaguchi
Masahiko, Yoshimoto
× Kosuke, Mizuno Yosuke, Terachi Kenta, Takagi Shintaro, Izumi Hiroshi, Kawaguchi Masahiko, Yoshimoto
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論文抄録 | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | This paper describes a Histogram of Oriented Gradients (HOG)-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40MHz for SVGA resolution video (800 × 600pixels) at 72 frames per second (fps). | |||||||
論文抄録(英) | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | This paper describes a Histogram of Oriented Gradients (HOG)-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40MHz for SVGA resolution video (800 × 600pixels) at 72 frames per second (fps). | |||||||
書誌情報 |
IPSJ Transactions on System LSI Design Methodology(TSLDM) 巻 6, p. 42-51, 発行日 2013-02-15 |
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ISSN | ||||||||
収録物識別子タイプ | ISSN | |||||||
収録物識別子 | 1882-6687 | |||||||
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言語 | ja | |||||||
出版者 | 情報処理学会 |