{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00089443","sets":["1164:1579:7041:7042"]},"path":["7042"],"owner":"11","recid":"89443","title":["コンパイラと協調したシミュレーション精度切り換え可能なマルチコアアーキテクチャシミュレータ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2013-01-24"},"_buckets":{"deposit":"87fb84a1-9ccf-4478-908a-0fad8597df0f"},"_deposit":{"id":"89443","pid":{"type":"depid","value":"89443","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"コンパイラと協調したシミュレーション精度切り換え可能なマルチコアアーキテクチャシミュレータ","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"コンパイラと協調したシミュレーション精度切り換え可能なマルチコアアーキテクチャシミュレータ"},{"subitem_title":"A Parallelizing Compiler Cooperative Multicore Architecture Simulator with Changeover Mechanism of Simulation Modes","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"モデリング・シミュレーション","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2013-01-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学"},{"subitem_text_value":"早稲田大学"},{"subitem_text_value":"早稲田大学"},{"subitem_text_value":"早稲田大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"WASEDA UNIVERSITY","subitem_text_language":"en"},{"subitem_text_value":"WASEDA UNIVERSITY","subitem_text_language":"en"},{"subitem_text_value":"WASEDA UNIVERSITY","subitem_text_language":"en"},{"subitem_text_value":"WASEDA UNIVERSITY","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/89443/files/IPSJ-ARC13203014.pdf"},"date":[{"dateType":"Available","dateValue":"2015-01-24"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC13203014.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"15640a7c-032e-4335-9edc-75364d38e110","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田口, 学豊"},{"creatorName":"阿部, 洋一"},{"creatorName":"木村, 啓二"},{"creatorName":"笠原, 博徳"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Gakuho, Taguchi","creatorNameLang":"en"},{"creatorName":"Youichi, Abe","creatorNameLang":"en"},{"creatorName":"Keiji, Kimura","creatorNameLang":"en"},{"creatorName":"Hironori, Kasahara","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では,コンパイラと協調してシミュレーション精度を相互に切り替えることができるマルチコアアーキテクチャシミュレータによってシミュレーション速度を高速化する枠組みを提案する.本提案では,コンパイラを介して,対象プログラムにおける詳細シミュレーションを行うサンプリング量の決定や,並列化プログラムに対する精度切り換えコードの自動生成を行う.本手法を SPEC CPU 2000 の EQUAKE に適用したところ,誤差 1.6 パーセント以内で 50 倍~ 500 倍の高速化が可能であることを示した.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A parallelizing compiler cooperative multicore architecture simulation framework, which enables reducing simulation time by a flexible simulation-mode changeover mechanism, is proposed. A multicore architecture simulator in this framework has two modes; namely, functional-and-fast simulation mode and cycle-accurate-and-slow simulation modes. This framework generates appropriate sampling points for cycle-accurate mode and runtime for mode changeover of the simulator depending on a parallelized application by cooperating with a parallelizing compiler. The proposed framework is evaluated with EQUAKE from SPEC2000. The evaluation result shows 50 times to 500 times speedup can be achieved within 1.6% error.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告計算機アーキテクチャ(ARC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2013-01-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"14","bibliographicVolumeNumber":"2013-ARC-203"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":89443,"updated":"2025-01-21T16:33:57.240633+00:00","links":{},"created":"2025-01-18T23:39:13.876918+00:00"}