{"id":86968,"updated":"2025-01-21T17:30:26.788559+00:00","links":{},"created":"2025-01-18T23:37:52.019250+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00086968","sets":["1164:2036:6668:6917"]},"path":["6917"],"owner":"11","recid":"86968","title":["WEBアプリ回路と直結したTCP/IPスタック回路の性能評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-11-19"},"_buckets":{"deposit":"fdacefe7-098c-4c68-bf39-cdba74d47acd"},"_deposit":{"id":"86968","pid":{"type":"depid","value":"86968","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"WEBアプリ回路と直結したTCP/IPスタック回路の性能評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"WEBアプリ回路と直結したTCP/IPスタック回路の性能評価"},{"subitem_title":"Performance evaluation of a TCP/IP Hardware Stack Directly Connectable to WEB Application Circuit","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"設計事例","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2012-11-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京農工大学工学府"},{"subitem_text_value":"東京農工大学工学府"},{"subitem_text_value":"東京農工大学工学府"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/86968/files/IPSJ-SLDM12158037.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM12158037.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"f62b5788-63a4-4723-bb8f-9fc23ce7a7fd","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2012 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"藤田, 琴子"},{"creatorName":"田向, 権"},{"creatorName":"関根, 優年"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kotoko, Fujita","creatorNameLang":"en"},{"creatorName":"Hakaru, Tamukoh","creatorNameLang":"en"},{"creatorName":"Masatoshi, Sekine","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々はこれまでに， FPGA で動作可能な TCP/IP スタック回路を設計し提案して，また，本稿では TOP/IP スタック回路と WEB ハード・ソフトウェアアプリを直結して動作させた結果を報告する．本方式によれば， CPU から TOP/IP 処理を完全に解放し，新しいプロトコルやアップデートにも柔軟に対応できる低価格 FPGA Xilinx Spartan3-2000 と 100BASE TX LAN PHY チップを用いた動作実験で，約 95Mbps の実効性能を達成し，その動的消費電力は約 33mV であった．また，動画像伸張圧縮回路と組み合わせ，フルカラー VGA 画像を圧縮．TOP/IP 通信．伸張したところ，約 21fps の実効性能を達成し，そのとぎの動的消費電力は約 96mW であった．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We have proposed a TCP/IP circuit and implemented it using a CardBus FPGA board. This paper proposes a TCP/IP hardware stack to allow direct connection of embedded application into the internet. It achieved maximum throughput of 95 Mbps with 100BASE TX LAN PHY chip and cosumed 33.06 mW dynamic power. We also develop a web streaming system by integrating the proposed TCP/IP and a video codec application circuit. The system achieved 21.2 frames per second of full color VGA streaming and consumed 95.7 mW when operating at 66 MHz and 3.3 V.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2012-11-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"37","bibliographicVolumeNumber":"2012-SLDM-158"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}