{"updated":"2025-01-21T17:29:26.387430+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00086933","sets":["1164:2036:6668:6917"]},"path":["6917"],"owner":"11","recid":"86933","title":["島内消費電力量見積もりにもとづく温度特性を考慮したRDRアーキテクチャ向け高位合成手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-11-19"},"_buckets":{"deposit":"cb9e793f-405a-4735-b1fd-6cb28cd3718e"},"_deposit":{"id":"86933","pid":{"type":"depid","value":"86933","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"島内消費電力量見積もりにもとづく温度特性を考慮したRDRアーキテクチャ向け高位合成手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"島内消費電力量見積もりにもとづく温度特性を考慮したRDRアーキテクチャ向け高位合成手法"},{"subitem_title":"A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"動作合成","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2012-11-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Grad. of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/86933/files/IPSJ-SLDM12158003.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM12158003.pdf","filesize":[{"value":"462.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6ab2619c-51f7-4066-a7fe-eb8b572151a9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2012 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川村, 一志"},{"creatorName":"柳澤, 政生"},{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kazushi, Kawamura","creatorNameLang":"en"},{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"},{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"半導体の微細化技術向上に伴い， IC チップ内部の発熱，特にホットスポットと呼ばれる局所的に温度の高い空間が問題となっている一方，微細化技術向上に伴ってゲート遅延より配線遅延が支配的となったため，高位合成段階で配線遅延を考慮する必要が生じている．これら双方の問題に対処するため，配線遅延を考慮した設計が可能な RDR アーキテクチャを対象に，温度特性を考慮した高位合成手法が提案された．本論文では，従来手法における島内消費電力量の見積もり式を改良し，島内消費電力量見積もりにもとづく温度特性を考慮した RDR アーキテクチャ向け高位合成手法を提案する RDR アーキテクチャはチップ内部を同じ面積の島に分割するため，提案手法では演算の実行回数に注目して島間の消費電力量を均一化し，ホットスポットの温度を削減する．さらに，レジスタやマルチプレクサがチップ内部の発熱に与える影響を見積もり， RDR アーキテクチャ上の空き領域に新たな演算器を配置することで，ホットスポットの温度最小化を図る．計算機実験により，提案手法は従来手法と比較して最大 15.51％ ホットスポットの温度を削減できることを確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"With process technology scaling, heat problems in IC chips as well as increasing the average interconnection delays are becoming serious issues. Recently, we have proposed a binding and allocation algorithm for regular-distributed-register architectures (RDR architectures) with the objective of minimizing the peak temperature. In this paper, we propose an improved thermal-aware high-level synthesis algorithm for RDR architectures. The RDR architecture divides the entire chip into islands regularly. Firstly, our algorithm balances the energy consumption among islands through re-binding to functional units. Secondly, it accurately estimates the energy consumption in each island and minimizes the maximum energy consumption among islands through re-allocating new additional functional units. Experimental results demonstrate that our algorithm reduces the peak temperature by up to 15.42% compared with the conventional approaches.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2012-11-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"2012-SLDM-158"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:37:50.316871+00:00","id":86933,"links":{}}