{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00086053","sets":["934:1119:6676:6895"]},"path":["6895"],"owner":"11","recid":"86053","title":["超低消費電力粗粒度再構成アクセラレータCMAのPEアレイアーキテクチャの最適化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-10-15"},"_buckets":{"deposit":"e9ee5d87-ac91-4171-a386-e5d94e866cf4"},"_deposit":{"id":"86053","pid":{"type":"depid","value":"86053","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"超低消費電力粗粒度再構成アクセラレータCMAのPEアレイアーキテクチャの最適化","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"超低消費電力粗粒度再構成アクセラレータCMAのPEアレイアーキテクチャの最適化"},{"subitem_title":"Optimization for PE Array Structure of Ultra Low Power Coarse-grained Reconfigurable Accelerator CMA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[省電力方式] リコンフィギャラブル,低電力","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2012-10-15","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/86053/files/IPSJ-TACS0505004.pdf"},"date":[{"dateType":"Available","dateValue":"2014-10-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS0505004.pdf","filesize":[{"value":"2.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d2f67c8d-73e1-4d9c-aaa6-9c0ba264bbaf","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2012 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小崎, 信明"},{"creatorName":"宇野, 理恵"},{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Nobuaki, Ozaki","creatorNameLang":"en"},{"creatorName":"Rie, Uno","creatorNameLang":"en"},{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"粗粒度再構成プロセッサは,アレイ状に配置された複数の PE (演算素子) を持ち, PE 間の接続網アーキテクチャは,デバイス全体の面積や消費電力,アプリケーションの構成情報の量に大きな影響を与える.本論文では,超低消費電力粗粒度再構成アクセラレータ CoolMega-Array (CMA) の PE アレイ接続網アーキテクチャの最適化について言及する.様々な接続網の CMA を設計し,面積,電力,構成情報量,アプリケーション搭載の柔軟性から最適な接続網アーキテクチャを検討する. CMA の接続網は定数専用リンクを設けたものが構成情報量が最も少なく, 1 つの SW から構成されるスイッチングエレメントのアイランドスタイルと 2 方向の直結網のハイブリッドで構成される CMA-Const-H が最も面積と電力を削減でき, CMA の試作機として開発された CMA-1 と比較して面積を 22%,消費電力では 23% 削減でき,構成情報量を最大で 63%,平均で 49% 削減し, PE の遅延時間もわずかに短縮することに成功した.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Coarse-grained reconfigurable processors consist of an array of processing elements (PEs), and PE array structure affects total device's area, performance, power consumption and context size. This paper investigates the optimized PE array structure of an ultra low power coarse-grained reconfigurable accelerator: Cool Mega-Array (CMA). CMAs with various connection networks and PE structures are designed and evaluated. CMA-Const-H in which PEs are connected by 1 set of switching element and has links dedicated for constant value, achieved the smallest power consumption and area. Compared with the first prototype CMA-1, CMA-Const-H reduced area by 22%, power consumption by 23%, context size by 63%, and the delay time a bit.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"22","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム(ACS)"}],"bibliographicPageStart":"10","bibliographicIssueDates":{"bibliographicIssueDate":"2012-10-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"5"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":86053,"updated":"2025-01-21T17:50:35.729070+00:00","links":{},"created":"2025-01-18T23:37:29.688988+00:00"}