{"updated":"2025-01-21T18:36:50.505711+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00083282","sets":["1164:2240:6731:6840"]},"path":["6840"],"owner":"11","recid":"83282","title":["メニーコアOS向け新プロセスモデルの提案"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-07-25"},"_buckets":{"deposit":"79825ae7-0524-48e8-bbe9-8f9eab94c6e1"},"_deposit":{"id":"83282","pid":{"type":"depid","value":"83282","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"メニーコアOS向け新プロセスモデルの提案","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"メニーコアOS向け新プロセスモデルの提案"},{"subitem_title":"A Proposal of A New Process Model for Many-Core Architectures","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"OS，処理系","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2012-07-25","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"独立行政法人理化学研究所計算科学研究機構"},{"subitem_text_value":"独立行政法人理化学研究所計算科学研究機構"},{"subitem_text_value":"独立行政法人理化学研究所計算科学研究機構"},{"subitem_text_value":"独立行政法人理化学研究所計算科学研究機構／東京大学情報基盤センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"RIKEN AICS","subitem_text_language":"en"},{"subitem_text_value":"RIKEN AICS","subitem_text_language":"en"},{"subitem_text_value":"RIKEN AICS","subitem_text_language":"en"},{"subitem_text_value":"RIKEN AICS／Information Technology Center, University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/83282/files/IPSJ-HPC12135003.pdf"},"date":[{"dateType":"Available","dateValue":"2014-07-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC12135003.pdf","filesize":[{"value":"761.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"7d15e2a8-8e7e-4133-9458-c3667baedea2","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2012 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"島田, 明男"},{"creatorName":"バリ, ゲローフィ"},{"creatorName":"堀, 敦史"},{"creatorName":"石川, 裕"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akio, Shimada","creatorNameLang":"en"},{"creatorName":"Balazs, Gerofi","creatorNameLang":"en"},{"creatorName":"Atsuhi, Hori","creatorNameLang":"en"},{"creatorName":"Yutaka, Ishikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"エクサスケールのスーパーコンピュータ実現に向けてメニーコアアーキテクチャが注目されている．メニーコア環境では，ノード内の計算処理の並列化が重要となる．本研究では，マルチプロセス型並列アプリケーションにおいて，低コストなプロセス間通信を実現するためのプロセスモデルとして，Partitioned Virtual Address Space (PVAS) を提案する．PVAS を用いることで，プロセス間通信で発生するコストを低減し，従来よりも効率的なノード内並列化を実現することができる．PVAS のプロセス間通信を利用する MPI 通信を実装し，評価したところ，通信のレイテンシとスループットを大幅に改善可能であることが分かり，本提案の有効性を確認することができた．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Many-core architectures are gathering attention toward Exa-scale computing. In many-core environments, intra-node parallelization is an important issue. In this paper, Partitioned Virtual Address Space (PVAS) that is a new process model for many-core architectures is proposed. PVAS provides the scheme for efficient inter-process communication to multi-process applications so that they can achieve high performance intra-node parallelization. The MPI communication library, which leverages the inter-process communication of PVAS, outperforms the original MPI in the evaluation of the intra-node communication.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2012-07-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"2012-HPC-135"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:36:50.760836+00:00","id":83282,"links":{}}