{"created":"2025-01-18T23:36:49.645373+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00083259","sets":["1164:1579:6652:6839"]},"path":["6839"],"owner":"11","recid":"83259","title":["TSVを用いる間接NoCの評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-07-25"},"_buckets":{"deposit":"56562221-b55a-467b-935a-1f57d33e2fd8"},"_deposit":{"id":"83259","pid":{"type":"depid","value":"83259","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"TSVを用いる間接NoCの評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"TSVを用いる間接NoCの評価"},{"subitem_title":"Evaluation of Indirect NoC using TSV","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アーキテクチャ評価","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2012-07-25","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/83259/files/IPSJ-ARC12201007.pdf"},"date":[{"dateType":"Available","dateValue":"2014-07-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC12201007.pdf","filesize":[{"value":"545.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"91e31094-0139-4d5d-bad4-a7c19cf8cb17","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2012 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"飯尾, 亮介"},{"creatorName":"平木, 敬"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryosuke, Iio","creatorNameLang":"en"},{"creatorName":"Kei, Hiraki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"シングルスレッド性能向上の鈍化によるメニーコアへの転換が行われつつあるパフォーマンススケーリングを得るために NoC に関して多くの研究がなされている．特に，半導体製造技術の向上により可能となったシリコン貫通電極 （TSV） による三次元積層を用いた 3D-NoC が注目されている．3D-NoC がもたらす利点の 1 つとして，リンクの長さを短くしレイテンシを小さくすることが可能である点が挙げられる．本論文では，その利点を Multistage Interconnection Network (MIN) に適用し，k-ary n-tree 及び Dragonfly についてのパフォーマンス及び資源消費に対する評価を行った．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently，the improvement of single thread performance has decreased．This has led to focus on multi thread performance on many cores．To obtain performance scaling，a lot of research have been performed．Due to the improvement of semiconductor manufacturing，3D stacking chips and 3D-NoC can be designed and developed using Through Silicon Via (TSV)．One of the advantages produced by it is to have the ability of reducing the length of links and the latency．In this paper，by adopting this advantage to Multistage Interconnection Network (MIN)，we evaluated k-ary n-tree and Dragonfly in terms of performance and resource consumption．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2012-07-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"2012-ARC-201"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":83259,"updated":"2025-01-21T18:38:29.831545+00:00","links":{}}