{"updated":"2025-01-21T18:38:27.910875+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00083258","sets":["1164:1579:6652:6839"]},"path":["6839"],"owner":"11","recid":"83258","title":["1600万計算コア超メニーコアアーキテクチャのシミュレーション"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-07-25"},"_buckets":{"deposit":"9483b407-4775-4280-8362-034a9cb8c63a"},"_deposit":{"id":"83258","pid":{"type":"depid","value":"83258","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"1600万計算コア超メニーコアアーキテクチャのシミュレーション","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"1600万計算コア超メニーコアアーキテクチャのシミュレーション"},{"subitem_title":"Simulation of a Many-Core Architecture with 16 Million Processing Cores","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アーキテクチャ評価","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2012-07-25","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/83258/files/IPSJ-ARC12201006.pdf"},"date":[{"dateType":"Available","dateValue":"2014-07-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC12201006.pdf","filesize":[{"value":"845.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9491b3ce-1e9a-4243-bb79-579d0525af4f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2012 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"泊, 久信"},{"creatorName":"平木, 敬"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hisanobu, Tomari","creatorNameLang":"en"},{"creatorName":"Kei, Hiraki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"8080 と SH-2 プロセッサを用い、メニーコアアーキテクチャで評価した。メニーコアでは、複雑なプロセッサコアを用いると搭載できるコア数が少なくなってしまうため、従来のプロセッサより小型のコアが用いられることがある。コア数を最大化するため単純化されたコアを用いると、コアあたりの性能が下がるため、コア数とコアあたりの性能を勘案して、性能の総和が大きくなるような設計にする必要がある。もっとも単純なプロセッサの一つである 8080 と、パイプライン動作をするが小型の実装が可能な SH-2 を用い、メニーコアアーキテクチャに当てはめて性能を評価することで、超メニーコア時代に最適なプロセッサコアのバランスを調べた。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"8080 and SH-2 processors are evaluated as building blocks for a many-core architecture．In many-core architecture processor core designs simpler than conventional ones are often used because the number of processing elements that are integrated on a chip is limited by the size of the processor core．A many-core system design intends to maximize the throughput of instruction execution through the balance between the number of processor cores and the performance of a processor core．We put the 8080，which is one of the simplest processors，and the SH-2 pipelined processor in our many-core design to examine the optimal balance of simplicity and performance for the processor core in many-core designs．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2012-07-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"6","bibliographicVolumeNumber":"2012-ARC-201"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:36:49.596946+00:00","id":83258,"links":{}}