{"updated":"2025-01-21T20:13:23.403126+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00079492","sets":["1164:2036:6262:6632"]},"path":["6632"],"owner":"10","recid":"79492","title":["An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-11-21"},"_buckets":{"deposit":"94778eb1-5a82-432e-a717-55a0e1455bcc"},"_deposit":{"id":"79492","pid":{"type":"depid","value":"79492","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations"},{"subitem_title":"An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"実装技術と低消費電力化","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2011-11-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Department of Communication and Integrated Systems, Tokyo Institute of Technology"},{"subitem_text_value":"Division of Electrical, Electronic and Information Engineering, Osaka University"},{"subitem_text_value":"Department of Communication and Integrated Systems, Tokyo Institute of Technology"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Communication and Integrated Systems, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Division of Electrical, Electronic and Information Engineering, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Department of Communication and Integrated Systems, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/79492/files/IPSJ-SLDM11153037.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM11153037.pdf","filesize":[{"value":"348.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"99f224f6-42f5-47c1-88f9-63840166198d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yiqiang, Sheng"},{"creatorName":"Atsushi, Takahashi"},{"creatorName":"Shuichi, Ueno"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yiqiang, Sheng","creatorNameLang":"en"},{"creatorName":"Atsushi, Takahashi","creatorNameLang":"en"},{"creatorName":"Shuichi, Ueno","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"The 3D packing for VLSI physical design is facing big challenges to get better solution quality with less computational time. In this paper, we propose 2-stage simulated annealing with crossover operator (2-SA-X) to solve a general rectangular 3D-packing problem by using sequence-k-tuple representation, where k is defined by 3 and 5. The basic ideas of this research are to reuse the information of past solution by integrating the crossover operator from genetic algorithm and to improve the global search ability by using two different stages. The first stage mainly focuses on the global search by moving methods with big changes, including the crossover, while the second stage focuses on local search by the moving methods with small changes. Based on the experiment using ami98_3D benchmark, the computational performance of 3D packing is considerably improved. The paper shows how much the 3D-packing ratio of volume and the computational time can be improved by using the proposed 2-SA-X algorithm, comparing with normal 2-stage simulated annealing (2-SA) without the crossover operator.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The 3D packing for VLSI physical design is facing big challenges to get better solution quality with less computational time. In this paper, we propose 2-stage simulated annealing with crossover operator (2-SA-X) to solve a general rectangular 3D-packing problem by using sequence-k-tuple representation, where k is defined by 3 and 5. The basic ideas of this research are to reuse the information of past solution by integrating the crossover operator from genetic algorithm and to improve the global search ability by using two different stages. The first stage mainly focuses on the global search by moving methods with big changes, including the crossover, while the second stage focuses on local search by the moving methods with small changes. Based on the experiment using ami98_3D benchmark, the computational performance of 3D packing is considerably improved. The paper shows how much the 3D-packing ratio of volume and the computational time can be improved by using the proposed 2-SA-X algorithm, comparing with normal 2-stage simulated annealing (2-SA) without the crossover operator.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2011-11-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"37","bibliographicVolumeNumber":"2011-SLDM-153"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"created":"2025-01-18T23:34:13.524445+00:00","id":79492,"links":{}}