{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00079491","sets":["1164:2036:6262:6632"]},"path":["6632"],"owner":"10","recid":"79491","title":["PCB一層配線における集合対間配線のフローを用いた配線長差削減アルゴリズム"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-11-21"},"_buckets":{"deposit":"4cde5121-2ab3-49a5-abd2-5875107a5d37"},"_deposit":{"id":"79491","pid":{"type":"depid","value":"79491","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"PCB一層配線における集合対間配線のフローを用いた配線長差削減アルゴリズム","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"PCB一層配線における集合対間配線のフローを用いた配線長差削減アルゴリズム"},{"subitem_title":"A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"実装技術と低消費電力化","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2011-11-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"大阪大学大学院工学研究科電気電子情報工学専攻"},{"subitem_text_value":"大阪大学大学院工学研究科電気電子情報工学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Division of Electrical， Electronic and Information Engineering Graduate School of Engineering，Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Division of Electrical， Electronic and Information Engineering Graduate School of Engineering，Osaka University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/79491/files/IPSJ-SLDM11153036.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM11153036.pdf","filesize":[{"value":"465.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"5ffff06a-493b-462c-ace9-ff7b943417c1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山本, 祐作"},{"creatorName":"高橋, 篤司"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yusaku, Yamamoto","creatorNameLang":"en"},{"creatorName":"Atsushi, Takahashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年の回路の高速化に伴い，信号の伝搬遅延を高い精度で実現することが求められている．プリント基板 (PCB) の配線設計においては配線長を制御することにより所望の伝搬遅延を実現する．本稿は，接続要求が端子間には与えられず，2 つの端子集合の間に与えられる集合対間配線問題おいて，配線長をできる限り精密に制御することを目的とし，総配線長最小の条件のもとで効率的に配線長差を削減するアルゴリズムを提案する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recent advances in circuit speed forces to realize signal propagation delay accurately. In PCB routing design, desired signal propagation delay is realized by controlling the wire length of a route. In this paper, for set pair routing problem in which connection requirements are given between a pair of terminal sets, an algorithm that reduces the length difference under the minimum total length constraint is proposed.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2011-11-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"36","bibliographicVolumeNumber":"2011-SLDM-153"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"id":79491,"updated":"2025-01-21T20:13:21.437541+00:00","links":{},"created":"2025-01-18T23:34:13.476488+00:00"}