{"created":"2025-01-18T23:33:33.412157+00:00","updated":"2025-01-21T20:37:33.432180+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00078142","sets":["1164:2036:6262:6560"]},"path":["6560"],"owner":"10","recid":"78142","title":["MBAFFおよびフィールド・ピクチャ構造対応Ｈ.264フルHD60i二倍速エンコーダIP"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-10-17"},"_buckets":{"deposit":"4257cbb0-b254-4c30-aad2-4cfbf4a2c8ac"},"_deposit":{"id":"78142","pid":{"type":"depid","value":"78142","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"MBAFFおよびフィールド・ピクチャ構造対応Ｈ.264フルHD60i二倍速エンコーダIP","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MBAFFおよびフィールド・ピクチャ構造対応Ｈ.264フルHD60i二倍速エンコーダIP"},{"subitem_title":"An H.264 Full HD 60i Double Speed Encoder IP Supporting Both MBAFF and Field-Pic Structure","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2011-10-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"株式会社東芝セミコンダクター＆ストレージ社半導体研究開発センター"},{"subitem_text_value":"株式会社東芝セミコンダクター＆ストレージ社半導体研究開発センター"},{"subitem_text_value":"株式会社東芝セミコンダクター＆ストレージ社半導体研究開発センター"},{"subitem_text_value":"株式会社東芝セミコンダクター＆ストレージ社半導体研究開発センター"},{"subitem_text_value":"株式会社東芝セミコンダクター＆ストレージ社半導体研究開発センター"},{"subitem_text_value":"株式会社東芝セミコンダクター＆ストレージ社半導体研究開発センター"},{"subitem_text_value":"株式会社東芝セミコンダクター＆ストレージ社,半導体研究開発センター，ロジックLSI事業部"},{"subitem_text_value":"株式会社東芝研究開発センター"},{"subitem_text_value":"株式会社東芝セミコンダクター＆ストレージ社半導体研究開発センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Center for Semiconductor Research & Development Semiconductor & Storage Products Company, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Center for Semiconductor Research & Development Semiconductor & Storage Products Company, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Center for Semiconductor Research & Development Semiconductor & Storage Products Company, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Center for Semiconductor Research & Development Semiconductor & Storage Products Company, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Center for Semiconductor Research & Development Semiconductor & Storage Products Company, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Center for Semiconductor Research & Development Semiconductor & Storage Products Company, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Center for Semiconductor Research & Development and Logic LSI Division, Semiconductor & Storage Products Company, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Research & Development Center Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Center for Semiconductor Research & Development Semiconductor & Storage Products Company, Toshiba Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/78142/files/IPSJ-SLDM11152005.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM11152005.pdf","filesize":[{"value":"345.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"58d19f4f-da93-4d99-b256-7e4296d18694","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Institute of Electronics, Information and Communication Engineers\nThis SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"森谷, 章"},{"creatorName":"松井, 一"},{"creatorName":"小川, 貴也"},{"creatorName":"望月, 厚志"},{"creatorName":"小玉, 翔"},{"creatorName":"狩野, 和代"},{"creatorName":"中山, 啓満"},{"creatorName":"古藤, 晋一郎"},{"creatorName":"石渡, 俊一"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Moriya","creatorNameLang":"en"},{"creatorName":"Hajime, Matsui","creatorNameLang":"en"},{"creatorName":"Takaya, Ogawa","creatorNameLang":"en"},{"creatorName":"Atsushi, Mochizuki","creatorNameLang":"en"},{"creatorName":"Sho, Kodama","creatorNameLang":"en"},{"creatorName":"Kazuyo, Kanou","creatorNameLang":"en"},{"creatorName":"Hiromitsu, Nakayama","creatorNameLang":"en"},{"creatorName":"Shinichiro, Koto","creatorNameLang":"en"},{"creatorName":"Shunichi, Ishiwata","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"今日、マルチメディアシステムや H.264 で符号化する多くの場合において、HD画像が幅広<使われている。しかしながら、H.264 の符号化処理では多くの計算やメモリアクセスを必要とするため、高性能な H.264 エンコーダを開発することは未だ困難である。本論文では、H.264 エンコーダの一例について述べる。本エンコーダは、フル HD 60i の画像を二倍速で符号化でき、インターレース画像における符号化ツールとして MBAFF とフィールド゜ピクチヤ構造をサポートしている。また、MBAFF を考慮した上でのパイプライン設計と階層型動き探索手法により、メモリバンド幅を削減している。本エンコーダは、6511nm CMOS テクノロジで 1637K の論理ゲート数と 336.5KB の on-chip SRAM で構成されている。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"HD video sequences are widely used in today's multimedia systems and many of these are encoded with H.264 codec. However, it is still challenging to develop a high-performance H.264 encoder because the H.264 encoding process needs a large amount of computations and memory accesses. In this paper, a novel H.264 encoder is described. This encoder can encode video sequences of full HD 60i at double speed. Both MBAFF and Field-Pic structure are supported as coding tool for interlaced video sequences. The memory bandwidths are reduced by using a hierarchical motion estimation method and a pipeline configuration with consideration of MBAFF. The encoder is implemented with 1637K logic gates and 336.5KB on-chip SRAM in the 65nm CMOS technology.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2011-10-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"2011-SLDM-152"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"id":78142,"links":{}}