{"updated":"2025-01-21T20:39:33.676457+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00078056","sets":["934:1119:6347:6556"]},"path":["6556"],"owner":"10","recid":"78056","title":["メニーコアプロセッサのための通信衝突に着目したタスク配置手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-10-05"},"_buckets":{"deposit":"8e5fd837-dd7d-4db1-8856-21f927b27ccd"},"_deposit":{"id":"78056","pid":{"type":"depid","value":"78056","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"メニーコアプロセッサのための通信衝突に着目したタスク配置手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"メニーコアプロセッサのための通信衝突に着目したタスク配置手法"},{"subitem_title":"A Task Mapping Method to Mitigate Network Contention for Many-core Processors","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2011-10-05","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学大学院情報理工学研究科"},{"subitem_text_value":"東京工業大学大学院情報理工学研究科"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Engineering, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/78056/files/IPSJ-TACS0404011.pdf"},"date":[{"dateType":"Available","dateValue":"2013-10-05"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS0404011.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"4529f412-1954-4dbd-92e1-1f37c138d58e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐野, 伸太郎"},{"creatorName":"吉瀬, 謙二"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shintaro, Sano","creatorNameLang":"en"},{"creatorName":"Kenji, Kise","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Network-on-Chip で接続されたコアを持つメニーコアアーキテクチャでは，並列化されたタスクのコアへの割り当て方によって性能が大きく変化する．そこで，自動的に最適なタスク配置を求めることが望まれる．本論文では，メニーコアプロセッサの性能向上を目指すタスク配置手法として，パターンに基づいた配置手法を提案する．シミュレータを用いた評価から，提案手法は NAS Parallel Benchmarks において有用性を確認した．","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The Network-on-Chip (NoC) is a promising interconnection for many-core processors. On the NoC-based manycore processors, the network performance of multi-thread programs depends on the method of task mapping. In this paper, we propose a pattern-based task mapping method in order to improve the performance of many-core processors. Evaluation of the proposed method using a detailed software simulator reveals effectiveness of the method.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"109","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム（ACS）"}],"bibliographicPageStart":"96","bibliographicIssueDates":{"bibliographicIssueDate":"2011-10-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"4","bibliographicVolumeNumber":"4"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"created":"2025-01-18T23:33:30.835057+00:00","id":78056,"links":{}}