{"created":"2025-01-18T23:32:46.408142+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00075745","sets":["1164:4088:6330:6499"]},"path":["6499"],"owner":"10","recid":"75745","title":["FPGAによるリングオシレータ型真性乱数生成器の性能向上"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-05-05"},"_buckets":{"deposit":"efcebb62-1948-4be4-af93-dc2d1f845f28"},"_deposit":{"id":"75745","pid":{"type":"depid","value":"75745","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"FPGAによるリングオシレータ型真性乱数生成器の性能向上","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAによるリングオシレータ型真性乱数生成器の性能向上"},{"subitem_title":"Performance enhancement of the ring oscillator type true random number generator on FPGA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2011-05-05","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"電気通信大学"},{"subitem_text_value":"電気通信大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Electro-Communications","subitem_text_language":"en"},{"subitem_text_value":"The University of Electro-Communications","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/75745/files/IPSJ-IOT11013019.pdf"},"date":[{"dateType":"Available","dateValue":"2013-05-05"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-IOT11013019.pdf","filesize":[{"value":"410.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"43"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"4efe0710-7f62-4f4d-b3a6-ee876426bf9b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"羽田, 和倫"},{"creatorName":"阿部, 公輝"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hada, Kazumichi","creatorNameLang":"en"},{"creatorName":"Abe, Koki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12326962","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGA 上で複数のリングオシレータを用いる乱数生成器として，各リングオシレータからの出力から排他的論理和を取り，その後にサンプリングする手法 (Sunar 型) と排他的論理和を取る前にフリップフロップ回路を用いて各リングオシレータからの出力をサンプリングする手法 (Wold 型) が知られている．本研究では，FPGA への実装において，配線の遅延のバラツキが小さくなるように，リングオシレータを構成するインバータの位置を指定する．得られた乱数列の乱数性評価を行った結果，Wold 型乱数生成器は，Sunar 型乱数生成器より乱数性が良いことを示す．さらに，リングオシレータの数が一定ならば，乱数性はリングオシレータの長さによらないことを示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Two types of true random number generators (TRNG) using a set of ring oscillators (ROs) are known: Sunar-type TRNG where outputs of ROs are directly XORed and sampled by a DFF and Wold-type TRNG where each output of an RO is sampled by a DFF before XORed. In this paper, inverters composing ROs are placed at specified positions when implementing a TRNG on an FPGA so as to minimize variations of wire delays between inverters. Evaluation results revealed that the randomness of Wold-type TRNG is better than that of Sunar-type TRNG. Furthermore, the randomness of Wold-type TRNG with a constant number of ROs does not depend on the length of ROs.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告インターネットと運用技術（IOT）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2011-05-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19","bibliographicVolumeNumber":"2011-IOT-13"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"id":75745,"updated":"2025-01-21T21:05:16.488923+00:00","links":{}}