Soft Error-Aware Scheduling in High-Level Synthesis

• Item type: SIG Technical Reports(1)
• 公開日: 2011-03-11
• タイトル: Soft Error-Aware Scheduling in High-Level Synthesis
• タイトル / 言語: en
• タイトル: Soft Error-Aware Scheduling in High-Level Synthesis
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 高位合成
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Research Fellow of the Japan Society for the Promotion of Science／Nagoya University／Ritsumeikan University
• 著者所属: Ritsumeikan University
• 著者所属: Ritsumeikan University
• 著者所属: Ritsumeikan University
• 著者所属: University of California, Irvine
• 著者所属: Nagoya University
• 著者所属(英): en
• 著者所属(英): Research Fellow of the Japan Society for the Promotion of Science / Nagoya University / Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): University of California, Irvine
• 著者所属(英): en
• 著者所属(英): Nagoya University
• 著者名: YukoHara-Azumi; Hiroyuki, Tomiyama; Takuya, Azumi; Shigeru, Yamashita; NikilD.Dutt; Hiroaki, Takada
• 著者名(英): Yuko, Hara-Azumi; Hiroyuki, Tomiyama; Takuya, Azumi; Shigeru, Yamashita; Nikil, D.Dutt; Hiroaki, Takada
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Due to the continuous reduction in chip feature size and supply voltage, soft errors are becoming a serious problem in the today's LSI design. This paper proposes a soft error-aware scheduling method in high-level synthesis. The reliability of the datapath circuit is determined not only by those of its computations, which depend on their assigned hardware resources, but also by those of its values, which are affected by their lifetime length. By considering both influences, our proposed method schedules operations for maximizing the reliability of the datapath circuit.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Due to the continuous reduction in chip feature size and supply voltage, soft errors are becoming a serious problem in the today's LSI design. This paper proposes a soft error-aware scheduling method in high-level synthesis. The reliability of the datapath circuit is determined not only by those of its computations, which depend on their assigned hardware resources, but also by those of its values, which are affected by their lifetime length. By considering both influences, our proposed method schedules operations for maximizing the reliability of the datapath circuit.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11451459
• 書誌情報: 研究報告システムLSI設計技術（SLDM）; 巻 2011-SLDM-149, 号 19, p. 1-6, 発行日 2011-03-11
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会