{"updated":"2025-01-21T21:36:40.150241+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00074403","sets":["6164:6165:6426:6428"]},"path":["6428"],"owner":"11","recid":"74403","title":["3次元積層SRAM/DRAMハイブリッド・キャッシュ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-05-18"},"_buckets":{"deposit":"158553ba-2286-4e0c-a269-4e495804d891"},"_deposit":{"id":"74403","pid":{"type":"depid","value":"74403","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"3次元積層SRAM/DRAMハイブリッド・キャッシュ","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"3次元積層SRAM/DRAMハイブリッド・キャッシュ"},{"subitem_title":"3 Dimensional Integrated SRAM/DRAM Hybrid Cache","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2011-05-18","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州大学大学院システム情報科学府"},{"subitem_text_value":"九州大学大学院システム情報科学府"},{"subitem_text_value":"九州大学大学院システム情報科学研究院"},{"subitem_text_value":"九州大学大学院システム情報科学研究院"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Electrical Engineering, Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Electrical Engineering, Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Information Science and Electrical Engineering, Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Information Science and Electrical Engineering, Kyushu University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/74403/files/IPSJ-SACSIS2011065.pdf"},"date":[{"dateType":"Available","dateValue":"2013-05-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SACSIS2011065.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"330","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"16"},{"tax":["include_tax"],"price":"330","billingrole":"11"},{"tax":["include_tax"],"price":"330","billingrole":"14"},{"tax":["include_tax"],"price":"330","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9380e9bd-6294-4721-be3b-e1bd7f1acf89","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"橋口, 慎哉"},{"creatorName":"福本, 尚人"},{"creatorName":"井上, 弘士"},{"creatorName":"村上, 和彰"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shinya, Hashiguchi","creatorNameLang":"en"},{"creatorName":"Naoto, Fukumoto","creatorNameLang":"en"},{"creatorName":"Koji, Inoue","creatorNameLang":"en"},{"creatorName":"Kazuaki, Murakami","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，3 次元積層 DRAM の利用を前提とし，大幅なチップ面積の増加を伴うことなく高いメモリ性能を達成可能な新しいキャッシュ・アーキテクチャを提案する．3 次元積層された DRAM を大容量キャッシュとして活用することで，オフチップメモリ参照回数の劇的な削減が期待できる．しかしながら，その反面，キャッシュの大容量化はアクセス時間の増加を招くため，場合によっては性能が低下する．この問題を解決するため，提案方式では，実行対象プログラムのワーキングセット・サイズに応じて 3 次元積層 DRAM キャッシュを選択的に活用する．ベンチマークプログラムを用いた定量的評価を行った結果，提案方式は動的制御方式で平均 15% の性能向上を達成した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes a novel cache architecture for 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Unfortunately, applying the 3D DRAM cache causes performance degradation for some programs, because increasing cache size makes access time longer. To tackle this issue, the proposed cache supports two operation modes: a fast but small SRAM cache mode and a slow but large DRAM cache mode. An appropriate operation mode is selected at run time based on the behavior of application programs. The evaluation results show that the proposed approach achieves 15% of memory performance improvement.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"315","bibliographic_titles":[{"bibliographic_title":"先進的計算基盤システムシンポジウム論文集"}],"bibliographicPageStart":"306","bibliographicIssueDates":{"bibliographicIssueDate":"2011-05-18","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2011"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:31:57.207479+00:00","id":74403,"links":{}}