{"links":{},"id":74348,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00074348","sets":["6164:6165:6426:6428"]},"path":["6428"],"owner":"11","recid":"74348","title":["MLPに着目したパイプライン化発行キューの動的サイジング"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-05-18"},"_buckets":{"deposit":"ece50928-8613-46d6-9215-a5b46a922a4c"},"_deposit":{"id":"74348","pid":{"type":"depid","value":"74348","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"MLPに着目したパイプライン化発行キューの動的サイジング","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MLPに着目したパイプライン化発行キューの動的サイジング"},{"subitem_title":"MLP-Aware Dynamic Sizing of Pipelined Issue Queue","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"マイクロアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2011-05-18","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋大学大学院工学研究科／現在，ローム(株)"},{"subitem_text_value":"名古屋大学大学院工学研究科"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Engineering, Nagoya University / Presently with Rohm Co., Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Nagoya University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/74348/files/IPSJ-SACSIS2011010.pdf"},"date":[{"dateType":"Available","dateValue":"2013-05-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SACSIS2011010.pdf","filesize":[{"value":"963.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"330","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"16"},{"tax":["include_tax"],"price":"330","billingrole":"11"},{"tax":["include_tax"],"price":"330","billingrole":"14"},{"tax":["include_tax"],"price":"330","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6d328aa1-ed58-4505-8b6d-afdf8804354e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"甲良, 祐也"},{"creatorName":"安藤, 秀樹"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuya, Kora","creatorNameLang":"en"},{"creatorName":"Hideki, Ando","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"メモリ・インテンシブなプログラムの実行時間を短くするアプローチとして，メモリ・レベル並列性 (MLP: memory-level parallelism) の利用は有効である．MLP 利用の 1 手法として，積極的なアウト・オブ・オーダ実行がある．このためには大きな発行キューが必要であるが，そのような発行キューはクロック速度を低下させるという問題がある．発行キューをパイプライン化すればこの問題を回避することができるが，発行が遅延し計算インテンシブなプログラムでは IPC が著しく低下するという問題が生じる．本論文では，MLP が利用可能なときのみ発行キューを拡大する動的サイジング手法を提案する．本手法は，MLP が利用可能かどうかを最終レベル・キャッシュのミスの生起によって予測あるいは判断し，発行キューをサイジングする．SPEC2000 ベンチマークを用いて評価した結果，提案の動的サイジング手法を用いれば，評価したほとんどのプログラムでサイズを固定した場合での最善の性能とほぼ同等かそれ以上の性能を達成できることを確認した．平均では，サイズを固定した場合での最善の性能より SPECint2000 で 0.7%，SPECfp2000 で 10.2%，両ベンチマーク・スイートで 11.1% 高い性能を達成した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Exploiting memory-level parallelism (MLP) is an effective approach to reduce execution time of memory-intensive programs. One of schemes to exploit MLP is aggressive out-oforder execution. For this, a large issue queue is required, but it degrades the clock rate. Although pipelining the issue queue solves this problem, it delays instruction issue and thus degrades IPC in compute-intensive programs dramatically. This paper proposes a dynamic sizing scheme that enlarges the issue queue only when MLP is exploitable. Our scheme changes the size of the issue queue by predicting or determing whether or not MLP is exploitable, based on occurence of the last-level cache misses. Our evaluation results using the SPEC2000 benchmark programs show that, in most programs, our dynamic sizing scheme achieves as well or better performance, compared with the best performance in a fixed-size issue queue. On an average, a processor with our scheme achieves 0.7%, 10.2%, or 11.1% higher performance, in SPECint2000, SPECfp2000, or both benchmark suites, respectively, over the best performance in a fixed-size issue queue.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"81","bibliographic_titles":[{"bibliographic_title":"先進的計算基盤システムシンポジウム論文集"}],"bibliographicPageStart":"72","bibliographicIssueDates":{"bibliographicIssueDate":"2011-05-18","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2011"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:31:54.579190+00:00","updated":"2025-01-21T21:35:04.321434+00:00"}