{"updated":"2025-01-21T21:43:56.549602+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00073981","sets":["1164:2036:6262:6407"]},"path":["6407"],"owner":"10","recid":"73981","title":["高位合成ツールを利用したハードウエアアルゴリズムの最適化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-05-11"},"_buckets":{"deposit":"ed909453-d63b-48b3-99cc-77220523cd68"},"_deposit":{"id":"73981","pid":{"type":"depid","value":"73981","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"高位合成ツールを利用したハードウエアアルゴリズムの最適化","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高位合成ツールを利用したハードウエアアルゴリズムの最適化"},{"subitem_title":"Optimization of Hardware Algorithms Utilizing a High Level Synthesis Tool","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"最適化技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2011-05-11","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科電気系工学専攻"},{"subitem_text_value":"東京大学大規模集積システム設計教育研究センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Electrical Engineering and Information Systems, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"VLSI Design and Education Center, The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/73981/files/IPSJ-SLDM11150010.pdf"},"date":[{"dateType":"Available","dateValue":"2013-05-11"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM11150010.pdf","filesize":[{"value":"201.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"230363e5-1e90-4b87-83a2-bfec6bd7dcf7","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"福井, 啓"},{"creatorName":"藤田, 昌宏"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Fukui","creatorNameLang":"en"},{"creatorName":"Masahiro, Fujita","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年大規模・高速化が求められる、HPC(High Performance Computing) の分野において、順調な大規模化が進む FPGA(Field Programmable Gate Array) を用いて実現しようという研究が報告されている。本研究は FPGA を用いて、特定分野における数値計算の高速化の実現を目指したものである。一般に計算アルゴリズムを FPGA 上で実装するには時間がかかる、また大きな労力が必要である。本研究では主要な計算部分はデータフローグラフを書くことによってハードウエアを記述できる高位合成ツールを用いており、開発期間の短さを利用して様々な実装の比較をした。本発表では、津波のシミュレータの実装を通して、様々な実装やアーキテクチャを速度の観点から比較をする。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently, there are some reports which suggest the utilization of FPGAs for HPC(High Performance Computing). The aim of this research is to accelerate specific calculatons. Generally, Development of FPGAs requires a long development term and a lot of labor. In this research, the main calculation part is designed utilizing a high level synthesis tool. In this paper, some different implementations of TUNAMI(tsunami simulator) are compared in terms of speed.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2011-05-11","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"10","bibliographicVolumeNumber":"2011-SLDM-150"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"created":"2025-01-18T23:31:43.901810+00:00","id":73981,"links":{}}