{"updated":"2025-01-21T23:39:12.363068+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00070047","sets":["1164:1579:5982:6141"]},"path":["6141"],"owner":"10","recid":"70047","title":["An Out-of-order Vector Processing Mechanism for Multimedia Applications"],"pubdate":{"attribute_name":"公開日","attribute_value":"2010-07-27"},"_buckets":{"deposit":"33122634-86a6-4927-a7fb-bfecda52eb7b"},"_deposit":{"id":"70047","pid":{"type":"depid","value":"70047","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"An Out-of-order Vector Processing Mechanism for Multimedia Applications","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"An Out-of-order Vector Processing Mechanism for Multimedia Applications"},{"subitem_title":"An Out-of-order Vector Processing Mechanism for Multimedia Applications","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2010-07-27","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Sciences, Tohoku University"},{"subitem_text_value":"Cyberscience Center, Tohoku University／JST CREST"},{"subitem_text_value":"Graduate School of Information Sciences, Tohoku University／JST CREST"},{"subitem_text_value":"Cyberscience Center, Tohoku University／JST CREST"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Sciences, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Cyberscience Center, Tohoku University / JST CREST","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Sciences, Tohoku University / JST CREST","subitem_text_language":"en"},{"subitem_text_value":"Cyberscience Center, Tohoku University / JST CREST","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/70047/files/IPSJ-ARC10190024.pdf"},"date":[{"dateType":"Available","dateValue":"2012-07-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC10190024.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"8b351d00-204c-4ae4-8c92-b77478d54e7d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2010 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ye, Gao"},{"creatorName":"Ryusuke, Egawa"},{"creatorName":"Hiroyuki, Takizawa"},{"creatorName":"Hiroaki, Kobayashi"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ye, Gao","creatorNameLang":"en"},{"creatorName":"Ryusuke, Egawa","creatorNameLang":"en"},{"creatorName":"Hiroyuki, Takizawa","creatorNameLang":"en"},{"creatorName":"Hiroaki, Kobayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Nowadays, multimedia applications (MMAs) form an important workload for general purpose processors. The vector processing is considered as the most potential approach for MMAs due to plenty of data level parallelism involved in them. However, the tradition vector architectures obey an in-order issue policy (IIP). The IIP issue policy blocks the following instructions to be issued, no matter whether they are ready to be issued or not. This paper proposes a media-oriented vector architectural extension with an out-of-order vector processing mechanism (OVPM). The OVPM overcomes the inefficiency on utilization of the memory bandwidth and vector functional units. As a result, the proposed architecture achieves a higher performance with lower hardware cost than the traditional one. This paper evaluates the proposed architecture with architectural design parameters and finds out the most efficient size for the vector architecture when performing MMAs.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Nowadays, multimedia applications (MMAs) form an important workload for general purpose processors. The vector processing is considered as the most potential approach for MMAs due to plenty of data level parallelism involved in them. However, the tradition vector architectures obey an in-order issue policy (IIP). The IIP issue policy blocks the following instructions to be issued, no matter whether they are ready to be issued or not. This paper proposes a media-oriented vector architectural extension with an out-of-order vector processing mechanism (OVPM). The OVPM overcomes the inefficiency on utilization of the memory bandwidth and vector functional units. As a result, the proposed architecture achieves a higher performance with lower hardware cost than the traditional one. This paper evaluates the proposed architecture with architectural design parameters and finds out the most efficient size for the vector architecture when performing MMAs.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"10","bibliographic_titles":[{"bibliographic_title":"研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2010-07-27","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"24","bibliographicVolumeNumber":"2010-ARC-190"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"created":"2025-01-18T23:29:21.879700+00:00","id":70047,"links":{}}