{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00068977","sets":["1164:2036:5978:6080"]},"path":["6080"],"owner":"10","recid":"68977","title":["リアルタイムオンチップネットワーク向け先読みアービトレーション機構付ルータの設計と実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2010-03-19"},"_buckets":{"deposit":"e22e4aaa-a4be-4bf3-930d-76e41e9ec0bf"},"_deposit":{"id":"68977","pid":{"type":"depid","value":"68977","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"リアルタイムオンチップネットワーク向け先読みアービトレーション機構付ルータの設計と実装","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"リアルタイムオンチップネットワーク向け先読みアービトレーション機構付ルータの設計と実装"},{"subitem_title":"Design and Implementation of a On-Chip Router with Pre-Arbitration Mechanism for Real-Time Systems","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ハードウェア","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2010-03-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部情報工学科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科開放環境科学専攻"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科開放環境科学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Information and Computer Science, Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Graduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":10,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/68977/files/IPSJ-SLDM10144009.pdf","label":"IPSJ-SLDM10144009"},"date":[{"dateType":"Available","dateValue":"2012-03-19"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM10144009.pdf","filesize":[{"value":"558.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"19dce0fe-6772-4dd9-b638-15b70f87869e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2010 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"笹川, 雄二郎"},{"creatorName":"向後, 卓磨"},{"creatorName":"山崎, 信行"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yujiro, Sasagawa","creatorNameLang":"en"},{"creatorName":"Takuma, Kogo","creatorNameLang":"en"},{"creatorName":"Nobuyuki, Yamasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Chip Multiprocessor（CMP） におけるコア数の増加に伴い，コア間の相互接続方式として Network-on-Chip（NoC） が注目を集めてきており，リアルタイムシステムにおいてもその有用性が期待される．NoC はバスと比較してバンド幅が大きい一方で，ルータ遅延を主要因とする大きな転送遅延を持つ．転送遅延を抑えるために，様々な低遅延ルータが提案されているが，現在提案されているルータの低遅延化手法はリアルタイム処理を考慮しておらず，リアルタイムシステム向けルータに適用した場合，優先度逆転問題が生じてしまう．本研究では，優先度逆転問題を生じさせずに，低遅延化を行うリアルタイムシステム向け先読みアービトレーション機構付ルータの設計および実装を行った．先読みアービトレーション機構付ルータと通常のルータの最高優先度パケットの転送遅延を比較した結果，7.6% の信号線の増加と 2.5% のルータ面積の増加で，最高優先度パケットの転送遅延を平均 8.1% 削減することができた．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Since the number of cores on a multi-processor is recently increasing, Network-on-Chips (NoC） is anticipated for method of interconnections between cores on a multi-processor and it is expected to come to support real-time systems. Although NoCs have higher bandwidth than buses, they have high transfer latency mainly depending on router latency. Although a number of low latency router is proposed to reduce transfer latency, they can cause priority inversion. In this paper, we design and implement a pre-arbitration router for realtime systems. The results of comparison between basic router and pre-arbitration router shows that the wire and area increases by 7.6% and 2.5% respectively, however the transfer latency of the highest priority packet is reduced by 8.1%.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2010-03-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"9","bibliographicVolumeNumber":"2010-SLDM-144"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"id":68977,"updated":"2025-01-21T22:21:57.208970+00:00","links":{},"created":"2025-01-18T23:28:32.227708+00:00"}