{"id":68236,"created":"2025-01-18T23:28:20.565126+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00068236","sets":["934:1160:6049"]},"path":["6049"],"owner":"10","recid":"68236","title":["Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems"],"pubdate":{"attribute_name":"公開日","attribute_value":"2010-02-15"},"_buckets":{"deposit":"b3057973-6ea0-494d-bd42-20c6f7b18788"},"_deposit":{"id":"68236","pid":{"type":"depid","value":"68236","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems"},{"subitem_title":"Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"System-level Verification","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2010-02-15","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Hiroshima City University"},{"subitem_text_value":"The University of Kitakyushu"},{"subitem_text_value":"System IP Core Laboratories, NEC Corporation"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Hiroshima City University","subitem_text_language":"en"},{"subitem_text_value":"The University of Kitakyushu","subitem_text_language":"en"},{"subitem_text_value":"System IP Core Laboratories, NEC Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/68236/files/IPSJ-TSLDM0300007.pdf"},"date":[{"dateType":"Available","dateValue":"2012-02-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0300007.pdf","filesize":[{"value":"385.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"762d3049-c611-4052-a32b-887f99f2b36f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2010 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masato, Inagi"},{"creatorName":"Yasuhiro, Takashima"},{"creatorName":"Yuichi, Nakamura"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masato, Inagi","creatorNameLang":"en"},{"creatorName":"Yasuhiro, Takashima","creatorNameLang":"en"},{"creatorName":"Yuichi, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Multi-FPGA prototyping systems are widely used to verify logic circuit designs. To implement a large circuit using such a system, the circuit is partitioned into multiple FPGAs. Subsequently, sub-circuits assigned to FPGAs are connected using interconnection resources among the FPGAs. Because of limited resources, time-multiplexed I/Os are used to accommodate all signals in exchange for system speed. In this study, we propose an optimization method of inter-FPGA connections for multi-FPGA systems with time-multiplexed I/Os to shorten the verification time by accelerating the systems. Our method decides whether each inter-FPGA signal is transferred by a normal I/O or a time-multiplexed I/O, which is slower than a normal I/O but can transfer multiple signals. Our method optimizes inter-FPGA connections not only between a single FPGA pair, but among all the FPGAs. Experiments showed that for four-way partitioned circuits, our method obtains an average system clock period 16.0% shorter than that of a conventional method.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Multi-FPGA prototyping systems are widely used to verify logic circuit designs. To implement a large circuit using such a system, the circuit is partitioned into multiple FPGAs. Subsequently, sub-circuits assigned to FPGAs are connected using interconnection resources among the FPGAs. Because of limited resources, time-multiplexed I/Os are used to accommodate all signals in exchange for system speed. In this study, we propose an optimization method of inter-FPGA connections for multi-FPGA systems with time-multiplexed I/Os to shorten the verification time by accelerating the systems. Our method decides whether each inter-FPGA signal is transferred by a normal I/O or a time-multiplexed I/O, which is slower than a normal I/O but can transfer multiple signals. Our method optimizes inter-FPGA connections not only between a single FPGA pair, but among all the FPGAs. Experiments showed that for four-way partitioned circuits, our method obtains an average system clock period 16.0% shorter than that of a conventional method.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"90","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology（TSLDM）"}],"bibliographicPageStart":"81","bibliographicIssueDates":{"bibliographicIssueDate":"2010-02-15","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"3"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"updated":"2025-01-22T00:16:58.878278+00:00","links":{}}