{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00066897","sets":["1164:2036:5619:5928"]},"path":["5928"],"owner":"10","recid":"66897","title":["FPGA実装を想定した束データ方式による非同期式回路のフロアプラン手法の検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2009-11-25"},"_buckets":{"deposit":"bf145a07-de1e-441c-8e3e-1cc96acd2e93"},"_deposit":{"id":"66897","pid":{"type":"depid","value":"66897","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"FPGA実装を想定した束データ方式による非同期式回路のフロアプラン手法の検討","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA実装を想定した束データ方式による非同期式回路のフロアプラン手法の検討"},{"subitem_title":"A Study of Floorplanning for Asynchronous Circuits with Bundled-data Implementation on FPGAs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"物理設計","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2009-11-25","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"会津大学"},{"subitem_text_value":"会津大学"},{"subitem_text_value":"国立情報学研究所"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Aizu","subitem_text_language":"en"},{"subitem_text_value":"The University of Aizu","subitem_text_language":"en"},{"subitem_text_value":"National Institute of Informatics","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":10,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/66897/files/IPSJ-SLDM09142025.pdf","label":"IPSJ-SLDM09142025"},"date":[{"dateType":"Available","dateValue":"2011-11-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM09142025.pdf","filesize":[{"value":"372.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"35607f2e-d98b-4795-9309-96645fe8e579","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2009 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"齋藤, 寛"},{"creatorName":"濱田, 尚宏"},{"creatorName":"米田, 友洋"},{"creatorName":"南谷, 崇"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroshi, Saito","creatorNameLang":"en"},{"creatorName":"Naohiro, Hamada","creatorNameLang":"en"},{"creatorName":"Tomohiro, Yoneda","creatorNameLang":"en"},{"creatorName":"Takashi, Nanya","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"束データ方式による非同期式回路において性能を決める要因は，遅延素子を含む制御回路の遅延である．したがって，実装の対象となる FPGA 上での制御回路の遅延を概算し，入力から出力までの制御回路の遅延の総和が最小となるようフロアプランを行う．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A factor to decide the performance of asynchronous circuits with bundleddata implementation is the delay of the control circuit including delay elements. This paper shows a floorplan method for bundled-data implementation so that the sum of control delays from inputs to outputs is minimized while estimating the control delays on the target FPGA.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2009-11-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"25","bibliographicVolumeNumber":"2009-SLDM-142"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"id":66897,"updated":"2025-01-21T22:22:12.365584+00:00","links":{},"created":"2025-01-18T23:27:31.692737+00:00"}