{"updated":"2025-01-22T01:06:42.684825+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00066237","sets":["934:1119:5602:5889"]},"path":["5889"],"owner":"10","recid":"66237","title":["SMTプロセッサにおけるL1/L2キャッシュアクセス動的切替え方式"],"pubdate":{"attribute_name":"公開日","attribute_value":"2009-09-18"},"_buckets":{"deposit":"91c8e243-5864-4301-87bb-a1c65b471fc8"},"_deposit":{"id":"66237","pid":{"type":"depid","value":"66237","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"SMTプロセッサにおけるL1/L2キャッシュアクセス動的切替え方式","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"SMTプロセッサにおけるL1/L2キャッシュアクセス動的切替え方式"},{"subitem_title":"Dynamic Switch Strategies of Accessing L1/L2 Cache for an SMT Processor","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2009-09-18","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京農工大学／日本学術振興会特別研究員PD／現在，任天堂株式会社"},{"subitem_text_value":"東京農工大学"},{"subitem_text_value":"東京農工大学"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Tokyo University of Agriculture and Technology / Research Fellow of the Japan Society for the Promotion of Science / Presently with Nintendo Co., Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/66237/files/IPSJ-TACS0203004.pdf"},"date":[{"dateType":"Available","dateValue":"2011-09-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS0203004.pdf","filesize":[{"value":"558.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"45856c2f-0aea-4bcc-a544-1132dd5bfae0","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2009 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小笠原, 嘉泰"},{"creatorName":"三輪, 忍"},{"creatorName":"中條, 拓伯"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yoshiyasu, Ogasawara","creatorNameLang":"en"},{"creatorName":"Shinobu, Miwa","creatorNameLang":"en"},{"creatorName":"Hironori, Nakajo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"SMTプロセッサは，複数のスレッドで演算器やキャッシュメモリを共有し，性能向上を目指している．ところが，キャッシュメモリの共有が原因で，キャッシュラインにおけるスレッド間競合が発生し，性能が低下するという問題がある．そこで本論文では，キャッシュアクセスとしてL2-ダイレクトアクセスを可能にし，それを適切な条件で適用することでL1-キャッシュメモリを使用するスレッド数を調節し，スレッド間競合を抑える．L1/L2キャッシュアクセスの動的切替え方式として，ヒット率を切替えパラメータとする方式とセットごとにキャッシュアクセスを切り替える方式を提案し，設計した．評価の結果，提案方式は通常のキャッシュアクセスと比較し，最大1.106倍，平均1.022倍の性能向上をもたらした．また，各提案方式を実装した結果，どちらの方式も，プロセッサとキャッシュメモリを含んだチップ全体で3%未満とわずかなハードウェア増加量で実現できることを示した．","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"An SMT processor aims to gain higher performance by sharing resources such as ALUs and cache memory among several threads. However, sharing cache memory causes thread conflict miss which degrades its performance. This paper proposes two dynamic switching strategies of accessing L1/L2 cache in order to improve performance. One uses the number of cache miss as switching, and the other switches accessing algorithm in each set. Dynamic switching strategies adjust number of thread in L1 Cache memory in order to reduce thread conflict miss. As a result, dynamic switching strategies show 1.022 times as high performance in average and 1.106 times in max as a conventional cache access. Furthermore, both dynamic switching strategies can be implemented with small additional hardware cost in less than 3%.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"25","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム（ACS）"}],"bibliographicPageStart":"12","bibliographicIssueDates":{"bibliographicIssueDate":"2009-09-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"2"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"created":"2025-01-18T23:27:06.968800+00:00","id":66237,"links":{}}