{"links":{},"id":66218,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00066218","sets":["934:1160:5887"]},"path":["5887"],"owner":"10","recid":"66218","title":["An Optimization Technique for Low-Energy Embedded Memory Systems"],"pubdate":{"attribute_name":"公開日","attribute_value":"2009-08-14"},"_buckets":{"deposit":"33bdfc15-daad-439e-88b6-49d120ed186f"},"_deposit":{"id":"66218","pid":{"type":"depid","value":"66218","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"An Optimization Technique for Low-Energy Embedded Memory Systems","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"An Optimization Technique for Low-Energy Embedded Memory Systems"},{"subitem_title":"An Optimization Technique for Low-Energy Embedded Memory Systems","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Circuit-Level Low-Power Design","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2009-08-14","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Electric Engineering, Kyushu University"},{"subitem_text_value":"System LSI Research Center, Kyushu University"},{"subitem_text_value":"Faculty of Information Science and Electric Engineering, Kyushu University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Electric Engineering, Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"System LSI Research Center, Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Information Science and Electric Engineering, Kyushu University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/66218/files/IPSJ-TSLDM0200022.pdf"},"date":[{"dateType":"Available","dateValue":"2009-08-14"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0200022.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"1b225fde-851e-4fa4-9953-adbf03d3c90c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2009 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tadayuki, Matsumura"},{"creatorName":"Tohru, Ishihara"},{"creatorName":"Hiroto, Yasuura"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tadayuki, Matsumura","creatorNameLang":"en"},{"creatorName":"Tohru, Ishihara","creatorNameLang":"en"},{"creatorName":"Hiroto, Yasuura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"On-chip memories generally use higher supply (<i>V<sub>DD</sub></i>) and higher threshold (<i>V<sub>th</sub></i>) voltages than those of logic parts to improve the static noise margin and to suppress the static energy consumption. However, the higher <i>V<sub>DD</sub></i> increases the dynamic energy consumption. This paper proposes a hybrid memory architecture which consists of the following two regions; (1) a dynamic energy conscious region which uses low <i>V<sub>DD</sub></i> and <i>V<sub>th</sub></i> and (2) a static energy conscious region which uses high <i>V<sub>DD</sub></i> and <i>V<sub>th</sub></i>. The proposed architecture is applied to a scratchpad memory. This paper also proposes an optimization problem for finding the optimal code allocation and the memory configuration simultaneously, which minimizes the total energy consumption of the memory under constraints of a static noise margin (SNM), a write margin (WM) and a memory access delay. The memory configuration is defined by a memory division ratio, a β ratio and a <i>V<sub>DD</sub></i>. Experimental results demonstrate that the total energy consumption of our original 90nm SRAM can be reduced by 62.9% at the best case with a 4.56% area overhead without degradations of SNM, WM and access delay.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"On-chip memories generally use higher supply (<i>V<sub>DD</sub></i>) and higher threshold (<i>V<sub>th</sub></i>) voltages than those of logic parts to improve the static noise margin and to suppress the static energy consumption. However, the higher <i>V<sub>DD</sub></i> increases the dynamic energy consumption. This paper proposes a hybrid memory architecture which consists of the following two regions; (1) a dynamic energy conscious region which uses low <i>V<sub>DD</sub></i> and <i>V<sub>th</sub></i> and (2) a static energy conscious region which uses high <i>V<sub>DD</sub></i> and <i>V<sub>th</sub></i>. The proposed architecture is applied to a scratchpad memory. This paper also proposes an optimization problem for finding the optimal code allocation and the memory configuration simultaneously, which minimizes the total energy consumption of the memory under constraints of a static noise margin (SNM), a write margin (WM) and a memory access delay. The memory configuration is defined by a memory division ratio, a β ratio and a <i>V<sub>DD</sub></i>. Experimental results demonstrate that the total energy consumption of our original 90nm SRAM can be reduced by 62.9% at the best case with a 4.56% area overhead without degradations of SNM, WM and access delay.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"249","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"239","bibliographicIssueDates":{"bibliographicIssueDate":"2009-08-14","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"created":"2025-01-18T23:27:06.065274+00:00","updated":"2025-01-22T01:08:01.635064+00:00"}