Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion

• Item type: Trans(1)
• 公開日: 2009-08-14
• タイトル: Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion
• タイトル / 言語: en
• タイトル: Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Architectural Low-Power Design
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Kyushu University
• 著者所属: Kyushu University
• 著者所属: Kyushu University
• 著者所属: Kyushu University
• 著者所属(英): en
• 著者所属(英): Kyushu University
• 著者所属(英): en
• 著者所属(英): Kyushu University
• 著者所属(英): en
• 著者所属(英): Kyushu University
• 著者所属(英): en
• 著者所属(英): Kyushu University
• 著者名: Seiichiro, Yamaguchi; Yuriko, Ishitobi; Tohru, Ishihara; Hiroto, Yasuura
• 著者名(英): Seiichiro, Yamaguchi; Yuriko, Ishitobi; Tohru, Ishihara; Hiroto, Yasuura
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a miss, at least one extra cycle is needed to access the L1-cache. This degrades the processor performance. Single-cycle-accessible Two-level Cache (STC) architecture proposed in this paper can resolve the problem in the conventional L0-cache based approach. Both a small L0 and a large L1 caches in our STC architecture can be accessed from an MPU core within a single cycle. A compilation technique for effectively utilizing the STC architecture is also presented in this paper. Experiments using several benchmark programs demonstrate that our approach reduces the energy consumption of memory subsystems by 64% in the best case and by 45% on an average without any performance degradation compared to the conventional L0-cache based approach.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a miss, at least one extra cycle is needed to access the L1-cache. This degrades the processor performance. Single-cycle-accessible Two-level Cache (STC) architecture proposed in this paper can resolve the problem in the conventional L0-cache based approach. Both a small L0 and a large L1 caches in our STC architecture can be accessed from an MPU core within a single cycle. A compilation technique for effectively utilizing the STC architecture is also presented in this paper. Experiments using several benchmark programs demonstrate that our approach reduces the energy consumption of memory subsystems by 64% in the best case and by 45% on an average without any performance degradation compared to the conventional L0-cache based approach.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 2, p. 189-199, 発行日 2009-08-14
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会