{"links":{},"id":66213,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00066213","sets":["934:1160:5887"]},"path":["5887"],"owner":"10","recid":"66213","title":["Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems"],"pubdate":{"attribute_name":"公開日","attribute_value":"2009-08-14"},"_buckets":{"deposit":"a5b797f3-b521-4c31-b8d2-3430a133b3e8"},"_deposit":{"id":"66213","pid":{"type":"depid","value":"66213","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems"},{"subitem_title":"Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"System-Level Low-Power Design","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2009-08-14","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Nagoya University"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/66213/files/IPSJ-TSLDM0200017.pdf"},"date":[{"dateType":"Available","dateValue":"2009-08-14"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0200017.pdf","filesize":[{"value":"697.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"54ca921d-fc98-40fa-803f-3baee047a1f2","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2009 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hideki, Takase"},{"creatorName":"Hiroyuki, Tomiyama"},{"creatorName":"Hiroaki, Takada"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hideki, Takase","creatorNameLang":"en"},{"creatorName":"Hiroyuki, Tomiyama","creatorNameLang":"en"},{"creatorName":"Hiroaki, Takada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Energy consumption has become one of the major concerns in modern embedded systems. Recently memory subsystems have become consumed large amount of total energy in the embedded processors. This paper proposes partitioning and allocation approaches of scratch-pad memory in non-preemptive fixed-priority multi-task systems. We propose three approaches (i.e., spatial, temporal, and hybrid approaches) which enable energy efficient usage of the scratch-pad region. These approaches can reduce energy consumption of instruction memory. Each approach is formulated as an integer programming problem that simultaneously determines (1) partitioning of the scratch-pad memory space for the tasks, and (2) allocation of functions to the scratchpad memory space for each task. Our formulations pay attention to the task periods for the purpose of energy minimization. The experimental results show up to 47% of energy reduction in the instruction memory subsystems can be achieved by the proposed approaches.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Energy consumption has become one of the major concerns in modern embedded systems. Recently memory subsystems have become consumed large amount of total energy in the embedded processors. This paper proposes partitioning and allocation approaches of scratch-pad memory in non-preemptive fixed-priority multi-task systems. We propose three approaches (i.e., spatial, temporal, and hybrid approaches) which enable energy efficient usage of the scratch-pad region. These approaches can reduce energy consumption of instruction memory. Each approach is formulated as an integer programming problem that simultaneously determines (1) partitioning of the scratch-pad memory space for the tasks, and (2) allocation of functions to the scratchpad memory space for each task. Our formulations pay attention to the task periods for the purpose of energy minimization. The experimental results show up to 47% of energy reduction in the instruction memory subsystems can be achieved by the proposed approaches.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"188","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"180","bibliographicIssueDates":{"bibliographicIssueDate":"2009-08-14","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"created":"2025-01-18T23:27:05.827940+00:00","updated":"2025-01-22T01:07:51.494214+00:00"}