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A GIDL-Current Model for Advanced MOSFET Technologies without Binning
https://ipsj.ixsq.nii.ac.jp/records/66205
https://ipsj.ixsq.nii.ac.jp/records/662053d3a793a-58ad-44e2-8fc7-0b57121ed6f4
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-TSLDM0200009.pdf (1.0 MB)
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Copyright (c) 2009 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | Trans(1) | |||||||
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| 公開日 | 2009-02-17 | |||||||
| タイトル | ||||||||
| タイトル | A GIDL-Current Model for Advanced MOSFET Technologies without Binning | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | A GIDL-Current Model for Advanced MOSFET Technologies without Binning | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | Device Modeling | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
| 資源タイプ | journal article | |||||||
| 著者所属 | ||||||||
| Waseda University / Semiconductor Technology Academic Research Center | ||||||||
| 著者所属 | ||||||||
| Hiroshima University | ||||||||
| 著者所属 | ||||||||
| Silvaco Japan Co., Ltd. | ||||||||
| 著者所属 | ||||||||
| Hiroshima University | ||||||||
| 著者所属 | ||||||||
| Waseda University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Waseda University / Semiconductor Technology Academic Research Center | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Hiroshima University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Silvaco Japan Co., Ltd. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Hiroshima University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Waseda University | ||||||||
| 著者名 |
Ryosuke, Inagaki
Norio, Sadachika
Dondee, Navarro
MitikoMiura-Mattausch
Yasuaki, Inoue
× Ryosuke, Inagaki Norio, Sadachika Dondee, Navarro MitikoMiura-Mattausch Yasuaki, Inoue
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| 著者名(英) |
Ryosuke, Inagaki
Norio, Sadachika
Dondee, Navarro
Mitiko, Miura-Mattausch
Yasuaki, Inoue
× Ryosuke, Inagaki Norio, Sadachika Dondee, Navarro Mitiko, Miura-Mattausch Yasuaki, Inoue
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | A GIDL (Gate Induced Drain Leakage) current model for advanced MOSFETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | A GIDL (Gate Induced Drain Leakage) current model for advanced MOSFETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AA12394951 | |||||||
| 書誌情報 |
IPSJ Transactions on System LSI Design Methodology （TSLDM） 巻 2, p. 93-102, 発行日 2009-02-17 |
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| ISSN | ||||||||
| 収録物識別子タイプ | ISSN | |||||||
| 収録物識別子 | 1882-6687 | |||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
