{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00061056","sets":["1164:1579:5607:5608"]},"path":["5608"],"owner":"10","recid":"61056","title":["メディアアプリケーションを用いた並列化コンパイラ協調型へテロジニアスマルチコアアーキテクチャのシミュレーション評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2009-01-06"},"_buckets":{"deposit":"3db32752-327b-4b66-afbe-8b9996d72efa"},"_deposit":{"id":"61056","pid":{"type":"depid","value":"61056","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"メディアアプリケーションを用いた並列化コンパイラ協調型へテロジニアスマルチコアアーキテクチャのシミュレーション評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"メディアアプリケーションを用いた並列化コンパイラ協調型へテロジニアスマルチコアアーキテクチャのシミュレーション評価"},{"subitem_title":"Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2009-01-06","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学理工学術院基幹理工学部情報理工学科"},{"subitem_text_value":"早稲田大学理工学術院基幹理工学部情報理工学科"},{"subitem_text_value":"早稲田大学理工学術院基幹理工学部情報理工学科"},{"subitem_text_value":"早稲田大学理工学術院基幹理工学部情報理工学科"},{"subitem_text_value":"早稲田大学理工学術院基幹理工学部情報理工学科"},{"subitem_text_value":"早稲田大学理工学術院基幹理工学部情報理工学科"},{"subitem_text_value":"早稲田大学理工学術院基幹理工学部情報理工学科"},{"subitem_text_value":"早稲田大学理工学術院基幹理工学部情報理工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":10,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/61056/files/IPSJ-ARC09181012.pdf","label":"IPSJ-ARC09181012"},"date":[{"dateType":"Available","dateValue":"2011-02-10"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC09181012.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9d7d466e-fed6-445b-a02a-050c8ced080b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2009 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"神山, 輝壮"},{"creatorName":"和田, 康孝"},{"creatorName":"林, 明宏"},{"creatorName":"間瀬, 正啓"},{"creatorName":"中野, 啓史"},{"creatorName":"渡辺, 岳志"},{"creatorName":"木村, 啓二"},{"creatorName":"笠原, 博徳"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Teruo, Kamiyama","creatorNameLang":"en"},{"creatorName":"Yasutaka, Wada","creatorNameLang":"en"},{"creatorName":"Akihiro, Hayashi","creatorNameLang":"en"},{"creatorName":"Masayoshi, Mase","creatorNameLang":"en"},{"creatorName":"Hirohumi, Nakano","creatorNameLang":"en"},{"creatorName":"Takeshi, Watanabe","creatorNameLang":"en"},{"creatorName":"Keiji, Kimura","creatorNameLang":"en"},{"creatorName":"Hironori, Kasahara","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，汎用プロセッサコアに加え複数のアクセラレータを 1 チップ上に集積したヘテロジニアスマルチコアアーキテクチャと，それに協調する自動並列化コンパイラの性能について述べる．コンパイラによる並列性の抽出を考慮して記述されたマルチメディアアプリケーションを用いて，汎用 CPU コアを 2 基， FE-GA を想定したアクセラレータコアを 2 基搭載したヘテロジニアスマルチコアアーキテクチヤ構成で評価したところ， ＭP3 エンコーダでは 1 つの汎用 CPU コアに対して 9.82 倍， JPEG 2000 エンコーダでは 14.64 倍 の速度向上率が得られた．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose cores, an automatic parallelizing compiler that cooperatively works with the heterogeneous multicore, a heterogeneous multicore architecture simulation environment, and performance evaluation results with the simulation environment. For the performance evaluation, multimedia applications written in C or Fortran, considered with parallelization by the compiler, are used. As a result, the evaluated heterogeneous multicore having two general purpose cores and two accelerator cores achieves 9.82 times speedup from MP3 encoder. This architecture also achieves 14.64 times speedup from JPEG2000 encoder. ","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"68","bibliographic_titles":[{"bibliographic_title":"研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"63","bibliographicIssueDates":{"bibliographicIssueDate":"2009-01-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1(2009-ARC-181)","bibliographicVolumeNumber":"2009"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"id":61056,"updated":"2025-01-21T22:16:53.498039+00:00","links":{},"created":"2025-01-18T23:23:20.204092+00:00"}