@article{oai:ipsj.ixsq.nii.ac.jp:00059750,
 author = {Yasushi, Hibino and Kazufumi, Watanabe and Ikuo, Takeuchi and Yasushi, Hibino and Kazufumi, Watanabe and Ikuo, Takeuchi},
 issue = {2},
 journal = {Journal of Information Processing},
 month = {Aug},
 note = {This paper describes a 32-bit LISP processor chip developed for the AI workstation ELIS with the multiple programming paradigm language TAO. The objective of this microprocessor is to realize an S-expression machine that can match the speed of conventional machines for compiled code execution. Architectural features are a repetitive structure for VLSI implementation of the tagged architecture and a dedicated datapath for list manipulation. All the processor functions are realized on a single VLSI chip that uses a 2-micron CMOS process. ELIS supports not only LISP but also multiple programming paradigms. The ELIS interpreter has a higher performance than that of any other dedicated machine on the market., This paper describes a 32-bit LISP processor chip developed for the AI workstation ELIS with the multiple programming paradigm language TAO. The objective of this microprocessor is to realize an S-expression machine that can match the speed of conventional machines for compiled code execution. Architectural features are a repetitive structure for VLSI implementation of the tagged architecture and a dedicated datapath for list manipulation. All the processor functions are realized on a single VLSI chip that uses a 2-micron CMOS process. ELIS supports not only LISP but also multiple programming paradigms. The ELIS interpreter has a higher performance than that of any other dedicated machine on the market.},
 pages = {156--164},
 title = {A 32-bit LISP Processor for the Al Workstation ELIS with a Multiple Programming Paradigm Language  TAO},
 volume = {13},
 year = {1990}
}