{"updated":"2025-01-22T05:55:47.734930+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00054349","sets":["1164:4842:4873:4875"]},"path":["4875"],"owner":"1","recid":"54349","title":["Handel - Cによる教育用マイクロプロセッサSEP - 3の設計と工数評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2003-10-17"},"_buckets":{"deposit":"7855cf4b-9906-43ac-8ae7-58d9bac48ad7"},"_deposit":{"id":"54349","pid":{"type":"depid","value":"54349","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"Handel - Cによる教育用マイクロプロセッサSEP - 3の設計と工数評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Handel - Cによる教育用マイクロプロセッサSEP - 3の設計と工数評価"},{"subitem_title":"A design and effort evaluation of educational processor \"SEP - 3\" by Handel - C","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2003-10-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"静岡大学大学院情報学研究科"},{"subitem_text_value":"静岡大学情報学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The Graduate school of information, Shizuoka university","subitem_text_language":"en"},{"subitem_text_value":"Fuculty of information, Shizuoka university","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/54349/files/IPSJ-CE03071002.pdf"},"date":[{"dateType":"Available","dateValue":"2005-10-17"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-CE03071002.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"19"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"eb9ad2a1-2ef4-4d75-a9c5-aad6ddd4c3b6","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2003 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山口, 直人"},{"creatorName":"塩見, 彰睦"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Naoto, Yamaguchi","creatorNameLang":"en"},{"creatorName":"Akichika, Shiomi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096193","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"SEP-3は、静岡大学情報科学科の計算機教育用に開発されたマイクロプロセッサである。現在は回路図入力によるボトムアップ式で設計演習を行なっている。一方、実際の設計現場では言語ベースのトップダウン式設計手法へのシフトが起きようとしており、本学の設計演習もこのような変化に対応する必要がある。そこで本研究では、Ｃ言語を拡張したHDLであるHandel-Cを用いたトップダウン方式のSEP設計方法を提案し、その工数を評価した結果を報告する。実験の結果、目標工数36時間未満を達成することができ、回路規模も現行の実験ボードに実装可能な規模であることが確認できた。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In our university, the design exercise of microprocessor SEP-3 for education using a schematic entry CAD is performed with bottom-up method. On the other hand, design site is try to change to top-down design method using C base hardware description language. We also have to apply to such change. In this paper, we propose the top-down design of SEP-3 using Handel-C, and describe the design effort. At the result, new design method needed 15 man-hour and required approximately 10,000 gates.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"12","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告コンピュータと教育（CE）"}],"bibliographicPageStart":"7","bibliographicIssueDates":{"bibliographicIssueDate":"2003-10-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"103(2003-CE-071)","bibliographicVolumeNumber":"2003"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T23:18:14.688551+00:00","id":54349,"links":{}}