@techreport{oai:ipsj.ixsq.nii.ac.jp:00044874,
 author = {葛毅 and 櫻井, 隆雄 and 阿部, 公輝 and 坂井, 修一 and Yi, Ge and Takao, Sakurai and Koki, Abe and Shuichi, Sakai},
 issue = {75(2004-CSEC-026)},
 month = {Jul},
 note = {RSA暗号の暗号化/複合処理で用いられる剰余乗算回路の有効な手法の一つである，除算に基づく回路構成法を高基数化して一般化した．そして高基数化による面積/速度のトレードオフを評価した．数表現には冗長２進表現を用い，法の倍数の選択には高基数SRT除算で一般的に用いられるテーブルではなく，同じ構造を維持して高基数化するのに適した算術演算による構成法を用いている．評価の結果，基数16では基数4に比べて約1.6倍の面積コストで，約1.5倍の速度向上が得られた．, Hardware organized modular multiplication based on division algorithm is one of the effective methods used for RSA encryption/decryption. This paper generalizes the hardware organization of the modular multiplication based on the higher-radix SRT division algorithm, and describes the area/time trade-off of the organization. For the number representation we used the signed-digit number system and for selecting the multiple of modular we employed the arithmetic operation instead of the conventional look-up table. The method based on the arithmetic operation is suitable for keeping the same structure over wide range of high radices. The result of the evaluation revealed that a radix-16 multiplier produced 1.5 times speedup at about 1.6 times area cost compared with radix-4 multiplier.},
 title = {RSA暗号処理における高基数剰余乗算回路},
 year = {2004}
}