{"created":"2025-01-18T23:02:36.228971+00:00","updated":"2025-01-22T15:29:21.085698+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00033875","sets":["1164:2822:2827:2828"]},"path":["2828"],"owner":"1","recid":"33875","title":["MIPS R3000プロセッサにおける細粒度動的スリーブ制御の実装と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-01-16"},"_buckets":{"deposit":"a234379f-990c-4e40-bfbc-58f4c2cd8bf3"},"_deposit":{"id":"33875","pid":{"type":"depid","value":"33875","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"MIPS R3000プロセッサにおける細粒度動的スリーブ制御の実装と評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MIPS R3000プロセッサにおける細粒度動的スリーブ制御の実装と評価"},{"subitem_title":"A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2008-01-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"芝浦工業大学"},{"subitem_text_value":"東京農工大学"},{"subitem_text_value":"東京農工大学"},{"subitem_text_value":"東京農工大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":" Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Shibaura Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/33875/files/IPSJ-EMB08007013.pdf"},"date":[{"dateType":"Available","dateValue":"2010-01-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB08007013.pdf","filesize":[{"value":"1.6 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正章"},{"creatorName":"中村, 宏"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Naomi, Seki","creatorNameLang":"en"},{"creatorName":"Lei, ZHAO","creatorNameLang":"en"},{"creatorName":"Jo, Kei","creatorNameLang":"en"},{"creatorName":"Daisuke, Ikebuchi","creatorNameLang":"en"},{"creatorName":"YU, KOJIMA","creatorNameLang":"en"},{"creatorName":"YOHEI, HASEGAWA","creatorNameLang":"en"},{"creatorName":"HlDEHARU, AMANO","creatorNameLang":"en"},{"creatorName":"TOSHIHIRO, KASHIMA","creatorNameLang":"en"},{"creatorName":"SEIDAI, TAKEDA","creatorNameLang":"en"},{"creatorName":"TOSHIAKI, SHIRAI","creatorNameLang":"en"},{"creatorName":"MlTUSTAKA, NAKATA","creatorNameLang":"en"},{"creatorName":"KlMIYOSHI, USAMI","creatorNameLang":"en"},{"creatorName":"TETSUYA, SUNATA","creatorNameLang":"en"},{"creatorName":",JUN, KANAI","creatorNameLang":"en"},{"creatorName":"MlTARO, NAMIKI","creatorNameLang":"en"},{"creatorName":"MASAAKI, KONDO","creatorNameLang":"en"},{"creatorName":"Hiroshi, NAKAMURA","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本報告はパワーゲーティング(PG)を使った演算器レベルでの動的スリーブ制御による消費電力削減機構の実装及び評価を行う。MIPSR3000のALUからシフタ、乗算器、除算器を分離し、それぞれを動的にパワーゲーテイングを行う。省電力化を施したR3000コアと16KBのL1キャッシュ、TLBをあわせて、ASPLA90nmで試作チップGeyser-Oとしてテープアウトした。Geyser-Oの性能、電力と面積をポストレイアウト後のシミュレーションにより評価した。この結果、4種類のアプケーションについてリーク電力は平均約47％減らすことができた。一方、スリーブ制御の実装によって生じたエリアオーバーヘッドは41％であった。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A processor with a novel fine grain power gating technique to save leakage power was designed and implemented. An execution unit is divided into four small units: multiplier, divider, shifter and others, the power of each unit is cut-off dynamically based on the op eration. We tape-outed the prototype chip Geyser-0, which provides R3000 Core with the power reduction technique, 16KB caches and TLB using 90nm CMOS technology. Evaluation results of four benchmark programs for embedded application show that 47% leakage power are reduced in avarage with 41% area overhead. ","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"76","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告組込みシステム（EMB）"}],"bibliographicPageStart":"71","bibliographicIssueDates":{"bibliographicIssueDate":"2008-01-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1(2008-EMB-007)","bibliographicVolumeNumber":"2007"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":33875,"links":{}}