{"links":{},"id":33870,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00033870","sets":["1164:2822:2827:2828"]},"path":["2828"],"owner":"10","recid":"33870","title":["動的切り替え可能なSIMD/MIMD型プロセッサにおけるMIMDコアの低コスト実現法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-01-15"},"_buckets":{"deposit":"6d8af072-997b-4397-91a1-fca0c345ab52"},"_deposit":{"id":"33870","pid":{"type":"depid","value":"33870","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"動的切り替え可能なSIMD/MIMD型プロセッサにおけるMIMDコアの低コスト実現法","author_link":["462081","462082","462080","462077","462083","462076","462079","462078"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"動的切り替え可能なSIMD/MIMD型プロセッサにおけるMIMDコアの低コスト実現法"},{"subitem_title":"Low-Cost Implementation of the MIMD Core For a Runtime Mode Switching SIMD/MIMD processor","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2008-01-15","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"NEC システムＩＰコア研究所"},{"subitem_text_value":"NEC システムＩＰコア研究所"},{"subitem_text_value":"NEC システムＩＰコア研究所"},{"subitem_text_value":"NEC システムＩＰコア研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"NEC　System IP Core Research Laboratories","subitem_text_language":"en"},{"subitem_text_value":"NEC　System IP Core Research Laboratories","subitem_text_language":"en"},{"subitem_text_value":"NEC　System IP Core Research Laboratories","subitem_text_language":"en"},{"subitem_text_value":"NEC　System IP Core Research Laboratories","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/33870/files/IPSJ-EMB08007008.pdf","label":"IPSJ-EMB08007008"},"date":[{"dateType":"Available","dateValue":"2010-01-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB08007008.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"da703a5c-be88-446b-bec1-3f54725da3eb","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2008 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"野本, 祥平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"京, 昭倫"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"古賀, 拓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"岡崎, 信一郎"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shohei, NOMOTO","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shorin, KYO","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takuya, KOGA","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shin’ichiro, OKAZAKI","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，自動車における，画像認識を用いた安全システムの普及が始まっている．これらのシステムでは，リアルタイムな画像認識を熱設計が厳しい車載環境で行う必要があるため，画像認識プロセッサには，高い演算性能のみならず低消費電力性が求められる．また，複雑化する画像認識アルゴリズムに対応するため，様々な粒度の並列性を活用でき，なおかつ高いコスト性能比を実現することも必要となる．こうした中で，著者らは，高並列 SIMDプロセッサによる低コスト・高性能・低消費電力と，MIMD プロセッサによる柔軟な並列性の活用の双方の性質を併せ持つプロセッサの実現を目標に研究開発を進めてきた．本稿では，上記性質を持つプロセッサの実現に向け，SIMDプロセッサのProcessing Element(PE)の回路資源に着目し，複数のPEを組み合わせて１つの MIMD コアを実現する実装方式を提案・評価する．具体的には，1)PE のメモリ・レジスタファイルを流用したキャッシュ機構，2)SIMD/MIMDコアにおけるデータパスの共有，3)PE 演算器群を流用した浮動小数点パス，を実現した．これらの実装方針をとることにより，動的切り替え可能なSIMD/MIMD型プロセッサを実現するための追加コストを，MIMDコア全体の回路規模の約 10％までに抑えることが出来ることを示した．これにより，低コスト・高性能・低消費電力・柔軟性を併せ持つ画像認識プロセッサの実現可能性を示した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Safety systems that use image recognition are starting to be used commercially in cars. Because such systems must perform real-time image recognition in a car environment that imposes severe heat design requirements, the image recognition processor has to realize both high operation performance and low power consumption. Moreover, in order to support increasingly complex image recognition algorithms, the system must support various granularity of parallelism as well as achieve high cost performance.  Against this backdrop, the authors have been working on the development of a system that achieves low cost, high performance, and low power consumption through the use of a highly parallel SIMD processor, as well as flexible parallelism through the use of a MIMD processor. This paper proposes and evaluates a method for realizing a MIMD core that combines multiple processing elements (PE), with particular focus on the circuit resources reuse of the PEs of the SIMD processor Concretely, a three-pronged approach was employed: 1) organizing of a cache mechanism using the memories and register files of PEs, 2) sharing the data paths between the SIMD and MIMD cores,and 3) realizing a floating point path by using the execution units of the PEs. Through this approach, the additional footprint cost required for the realization of a dynamically switched SIMD/MIMD processor was successfully reduced to approximately 10% of the total circuit area of the MIMD core. This demonstrates the feasibility of highly competitive image recognition processors that combine low cost, high performance, low power consumption, and flexibility.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"46","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告組込みシステム（EMB）"}],"bibliographicPageStart":"41","bibliographicIssueDates":{"bibliographicIssueDate":"2008-01-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1(2008-EMB-007)","bibliographicVolumeNumber":"2007"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"created":"2025-01-18T23:02:36.009232+00:00","updated":"2025-01-19T23:20:12.769081+00:00"}