@techreport{oai:ipsj.ixsq.nii.ac.jp:00032848,
 author = {諏佐, 達也 and 村川, 正宏 and 高橋, 栄一 and 古谷, 立美 and 樋口, 哲也 and 古市, 愼治 and 上田, 佳孝 and 和田, 淳 and Tatsuya, Susa and Masahiro, Murakawa and Eiichi, Takahashi and Tatsumi, Furuya and Tetsuya, Higuchi and Shinji, Furuichi and Yoshitaka, Ueda and Atsushi, Wada},
 issue = {85(2008-MPS-071)},
 month = {Sep},
 note = {製造ばらつきにより発生するクロック・スキューの問題を解決するための手法として，遺伝的アルゴリズムを用いたディジタル LSI の製造後クロック調整技術が提案されている．しかし，調整後のチップの一部で不安定な動作が確認されるという問題点がある．これは電源電圧や温度などの環境変動が原因と考えられる．そこで本研究では，動作想定条件よりも厳しい条件で調整することによりタイミング余裕を確保し，更に， GA の終了条件を段階的に厳しくすることで限られた調整時間内で環境変動に対する頑極性を向上させうるディジタル LSI の製造後クロック調整手法を提案する．実用的回路の設計データを用いた調整シミュレーション実験の結果，タイミング余裕を確保した上で歩留を向上させることに成功した．, As LSI devices are increasingly implemented with finer patterns (below 100nm) and oper ating at faster clocks, the problem of fluctuations in clodc timing (also known as the "clock skew" problem) becomes even more crucial. In order to solve the problems associated with clock timing, our group has proposed a Genetic Algorithm (GA) based clock adjustment method. Although the GA successfully adjusted the clock timing of the teat chips, some of the adjusted chips were found to operate at lower levels of accuracy. This is because the clock timings were adjusted to the very margins of feasible timings to pass the ninction tests. To overcome this difficulty, we propose an improved GA-based clock adjustment method which ensures that the adjustment results are sufficiently robust to cope with fluctuations in the LSI environment. Adjustment experiments using the developed simulator demonstrate that our method can enhance the operational yield while maintaining adequate operational tuning margins.},
 title = {動作マージンを確保可能なディジタルLSIの製造後クロック調整手法の提案},
 year = {2008}
}