{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00032642","sets":["1164:2592:2714:2717"]},"path":["2717"],"owner":"1","recid":"32642","title":["ジョグ挿入を伴ったチップ・コンパクション・アルゴリズム"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-07-16"},"_buckets":{"deposit":"16f510cc-6003-4603-9f32-9083c4cb03c9"},"_deposit":{"id":"32642","pid":{"type":"depid","value":"32642","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"ジョグ挿入を伴ったチップ・コンパクション・アルゴリズム","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ジョグ挿入を伴ったチップ・コンパクション・アルゴリズム"},{"subitem_title":"A Chip Compaction Algorithm with Jog Insertion","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1990-07-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"拓殖大学工学部情報工学科"},{"subitem_text_value":"早稲田大学理工学部電子通信学科"},{"subitem_text_value":"現在、ソニー（株）厚木テクノロジーセンター"},{"subitem_text_value":"早稲田大学理工学部電子通信学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Information Engineering, Takushoku University","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronics and Communication Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"has joined Atsugi Technology Center, Sony Corporation","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronics and Communication Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/32642/files/IPSJ-AL90016011.pdf"},"date":[{"dateType":"Available","dateValue":"1992-07-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-AL90016011.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"9"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"fbe0e302-5c92-43c9-a355-513bd9657394","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1990 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐藤政生"},{"creatorName":"山元, 渉"},{"creatorName":"中島, 伸佳"},{"creatorName":"大附, 辰夫"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masao, Sato","creatorNameLang":"en"},{"creatorName":"Wataru, Yamamoto","creatorNameLang":"en"},{"creatorName":"Nobuyoshi, Nakajima","creatorNameLang":"en"},{"creatorName":"Tatsuo, Ohtsuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN1009593X","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"電子回路をいかに小さい面積で設計するかがLSI設計の鍵である。そのために十数年前より、与えられたレイアウトを一方向に圧縮（コンパクション）する手法に関する研究が活発に行われている。レイアウト面積は配線の折り曲げ（ジョグ）を許してでも小さくすることが好ましい。チャネルに対しては有効なジョグを挿入しながら短時間のうちにコンパクションを行う手法が知られているが、チップ全体に対してはそのような手法は提案されていない。そこで本稿では、上下制約グラフ上で最短径路探索を行うことにより、ジョグ挿入を伴ったチップ・コンパクションを行う高速手法を提案する。また、計算機実験を行った結果を報告する。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The one-dimensional compaction is one of the most important tools to design dense LSI chips. To make the chips smaller by the compaction, jog insertion is quite effective. A new fast chip compaction algorithm with automatic jog insertion is presented in this paper. The algorithm is based on Dijkstra's shortest path algorithm on a constraint graph, which is derived from an input layout. Experimental results are also shown.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"84","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告アルゴリズム（AL）"}],"bibliographicPageStart":"77","bibliographicIssueDates":{"bibliographicIssueDate":"1990-07-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"58(1990-AL-016)","bibliographicVolumeNumber":"1990"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":32642,"updated":"2025-01-22T16:05:16.913717+00:00","links":{},"created":"2025-01-18T23:01:41.016563+00:00"}